2023 IEEE International Memory Workshop (IMW)最新文献_第4页

Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash Memory 提高3-D NAND快闪记忆体的电离辐射耐受性

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145957

B. Ray, Matchima Buddhanoy, Mondol Anik Kumar

引用次数: 0

Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications 用于超高速缓存和神经形态计算应用的自旋轨道扭矩MRAM

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145991

Siddharth Rao, K. Cai, G. Talmelli, Nathali Franchina-Vergel, Ward Janssens, H. Hody, F. Yasin, K. Wostyn, S. Couet

引用次数: 0

Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing 基于互补电阻开关的内存计算关联电容网络中电容潜行路径的消除

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145947

Tobias Ziegler, Leon Brackmann, T. Hennen, C. Bengel, S. Menzel, D. Wouters

引用次数: 0

7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology 7-Bit/2Cell (X3.5)， 9-Bit/2Cell (X4.5) NAND闪存:半比特技术

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145980

N. Shibata, H. Uchikawa, Taira Shibuya, Kenri Nakai, K. Yanagidaira, H. Inoue

{"title":"7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology","authors":"N. Shibata, H. Uchikawa, Taira Shibuya, Kenri Nakai, K. Yanagidaira, H. Inoue","doi":"10.1109/IMW56887.2023.10145980","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145980","url":null,"abstract":"In this work, a 3. 5bit/cell (X3.5) flash memory is introduced to achieve a lower giga-byte cost with high reliability and performance. Accordingly, 7-bit data are stored in two memory cells with 12-level Vth distributions. The X3.5 Programming method does not require the complex approach used in QLC and can easily be handled by NAND controller. QLC needs a more powerful ECC than TLC; hence, increasing the size of the ECC parity for QLC enlarges the die size. However, the same ECC parity size as TLC can be applicable to X3.5. An X3.5 die size with a TLC ECC is only 6.3% bigger than QLC. By contrast, X3.5 Program performance is 2.3 times faster than QLC with the QLC reliability criteria, which is relaxed from the TLC reliability criteria. If the size of the ECC parity is reduced to that of 32nmMLC, X3.5 die size will be close to that of QLC, while X3.5 Program performance will be 1.6 times faster than that of QLC. Moreover, X3.5 will meet the TLC reliability criteria. In addition to expanding X3.5 technologies, 4.5 bit/cell (X4.5) with a 24-level Vth distributions is also possible, which is suitable for cold storage applications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115018840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Materials Enabled Memory Scaling and New Architectures 材料支持内存缩放和新架构

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145976

Zhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran

引用次数: 0

Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering 通过读取方案优化和界面工程提高igzo沟道效应场效应管的毫瓦值

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145930

Zhuo Chen, N. Ronchi, A. Walke, K. Banerjee, M. Popovici, K. Katcko, G. V. D. Bosch, M. Rosmeulen, V. Afanas’ev, J. V. Houdt

引用次数: 1

An 18nm ePCM with BJT selector NVM design for advanced microcontroller applications 具有BJT选择器的18nm ePCM，用于高级微控制器应用

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145983

A. Conte, Francesco Tomaiuolo, Marco Ruta, A. Redaelli, F. Arnaud, T. Jouanneau, C. Boccaccio, O. Weber

引用次数: 0

Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance 基于随机计算的dnn内存计算(SC CiM)体系结构及非易失性存储器容错和缺陷容错的分层评估

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145982

Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, C. Matsui, Ken Takeuchi

{"title":"Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance","authors":"Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, C. Matsui, Ken Takeuchi","doi":"10.1109/IMW56887.2023.10145982","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145982","url":null,"abstract":"A Stochastic Computing-based Computation-inMemory architecture (SC CiM) with non-volatile memory (NVM) stochastic weights has been proposed. Both of the input and weight values are converted into stochastic bit streams. The multiply-and-accumulate (MAC) operation of the SC multiplication is performed in memory. The computational accuracy is characterized for Resnet-56 and CIFAR-10, with the bit error rate (BER) range from 1$0^{-4}$ to 1$0^{-2}$ representing the actual NVM characteristics. The effects of NVM BER are analyzed hierarchically at all computational layers (bit streams, MAC calculation and DNN inference) and compared both qualitatively and quantitatively with the conventional CiM. The results show the excellent robustness of the proposed SC CiM architecture in the wide range of BER. The tolerance to the manufacturing defects is even better than that of the conventional CiM. Furthermore, the desired weight distributions are discussed by exploiting the unique behaviors against NVM BER in the SC CiM.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128034778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation 三维可堆叠 1T1C DRAM：架构、工艺集成和电路仿真

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145931

Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo

{"title":"A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation","authors":"Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo","doi":"10.1109/IMW56887.2023.10145931","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145931","url":null,"abstract":"Continuous shrinking of dynamic random access memory $langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128387838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND 三维NAND中铁电增强栅极堆的保持优化

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145986

L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen

引用次数: 0