L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen
{"title":"三维NAND中铁电增强栅极堆的保持优化","authors":"L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen","doi":"10.1109/IMW56887.2023.10145986","DOIUrl":null,"url":null,"abstract":"In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND\",\"authors\":\"L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen\",\"doi\":\"10.1109/IMW56887.2023.10145986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.\",\"PeriodicalId\":153429,\"journal\":{\"name\":\"2023 IEEE International Memory Workshop (IMW)\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Memory Workshop (IMW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW56887.2023.10145986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND
In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.