2023 IEEE International Memory Workshop (IMW)最新文献_第3页

Low Power and Thermal Throttling-less SSD with In-Package Boost Converter for 1000-WL Layer 3D Flash Memory 低功耗和无热节流SSD与封装升压转换器用于1000-WL层3D闪存

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145971

Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, T. Miyazaki, Hideko Mukaida, M. Koyanagi, Masayuki Miura, T. Sanuki

{"title":"Low Power and Thermal Throttling-less SSD with In-Package Boost Converter for 1000-WL Layer 3D Flash Memory","authors":"Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, T. Miyazaki, Hideko Mukaida, M. Koyanagi, Masayuki Miura, T. Sanuki","doi":"10.1109/IMW56887.2023.10145971","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145971","url":null,"abstract":"Power consumption and thermal throttling of the 3D flash memory have become a prevalent issue owing to the requirement for higher performance in SSDs. One of the main causes is the on-die charge pump circuit, which has a low conversion efficiency and induces high heat generation. The heat generation becomes a critical issue due to the high-density mounting of components, especially in mobile products. In this work, we fabricated a 3D flash memory with an in-package boost converter to replace the on-die charge pump circuit. The boost converter consists of three types of discrete components: a DC-DC converter, an inductor, and capacitors. Using the in package boost converter, we show that the power consumption can be reduced by up to 39% while the temperature rise can be reduced by 50%. Furthermore, when the number of word line (WL) layers reaches 1000, a significantly large power reduction up to 43% can be achieved, resulting in 9% smaller power consumption compared to the conventional 1xx layers. The proposed in-package boost converter is an effective scheme to suppress the power consumption and heat generation and can realize the development of a thermal throttling-less SSD.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"399 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications 基于优化工艺的OTS-PCM存储器柱尺寸的综合研究以及用于SCM应用的低于10nm的缩放趋势

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145816

W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung

引用次数: 0

Overlay Control in HAR device integration HAR设备集成中的覆盖控制

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145953

P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie

{"title":"Overlay Control in HAR device integration","authors":"P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie","doi":"10.1109/IMW56887.2023.10145953","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145953","url":null,"abstract":"In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117129689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hafnium oxide-based Ferroelectric Memories: Are we ready for Application? 基于氧化铪的铁电存储器:我们准备好应用了吗?

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145945

K. Seidel, D. Lehninger, F. Müller, Y. Raffel, A. Sünbül, Ricardo Revello, R. Hoffmann, S. De, T. Kämpfe, M. Lederer

引用次数: 1

28nm Data Memory with Embedded RRAM Technology in Automotive Microcontrollers 基于嵌入式RRAM技术的28nm数据存储器应用于汽车微控制器

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145951

Alessandro Grossi, M. Coppetta, S. Aresu, A. Kux, T. Kern, R. Strenz

引用次数: 0

Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature Stress 具有改善偏置和温度应力下漏损的铁电HfO2/ZrO2超晶格

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145927

D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer

{"title":"Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature Stress","authors":"D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer","doi":"10.1109/IMW56887.2023.10145927","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145927","url":null,"abstract":"Abstract-Many modern applications require fast, reliable, and energy-efficient non-volatile memories. Ferroelectric memories like the ferroelectric field effect transistor (FeFET) and the ferroelectric random access memory (FeRAM) are promising to meet these requirements. In particular, the automotive sector places additional high demands in terms of reliability at high operation temperatures up to 150°C. Ferroelectric superlattices consisting of a periodic arrangement of HfO2 and ZrO2 sublayers are promising to meet these requirements. Herein, such superlattices of various sublayer thicknesses and a constant total thickness of $10 mathrm{~nm}$ were embedded into metal-ferroelectricmetal (MFM) capacitors and electrically characterized regarding compliance with the desired ambient temperature specifications of the automotive market. It is shown that superlattices with relatively thick sublayers ($geq 1 mathrm{~nm}$) significantly outperform standard $10 mathrm{~nm}(mathrm{Hf}, mathrm{Zr}) mathrm{O}_{2}$ reference films in terms of leakage resistance at demanding bias and temperature stress conditions.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134382142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production 量产第7代1Tb四阶单元3D NAND快闪记忆体的制程改进

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145937

Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyung-Hee Kim, Sejie Takaki, Y. Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, K. Noh, Sungjin Ahn, Sunghoi Hur

引用次数: 1

SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories 商用48层和96层3D-NAND闪存中的SLC和MLC内存近似搜索解决方案

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145964

P. Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, F. Lee, Yu-Yu Lin, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu

引用次数: 0

Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement DRAM存储电容器的介电弛豫性能及改进方法

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145928

Z. A. Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao

{"title":"Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement","authors":"Z. A. Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao","doi":"10.1109/IMW56887.2023.10145928","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145928","url":null,"abstract":"Dielectric relaxation in high-κ storage capacitors can lead to significant degradation of capacitance values and hence deteriorate read bit-error rates of DRAMs. However, the mechanism of the dielectric relaxation phenomenon in high-κ dielectric oxides and multilayer stacks is still controversial. Moreover, previous work studied the dielectric relaxation phenomenon only at high-κ film level, which lacks the necessary insights into DRAM-specific complexities and performance improvement strategies. In this work, we first set up modeling and electric testing methodologies that can reliably collect and model dielectric relaxation signal in modern DRAM high-κ capacitors at both single-cell and chip levels. Experiment and simulation evidences based on these methodologies were then presented to identify and validate charge trapping-detrapping as the physical origin of dielectric relaxation in the frequency realm of DRAM operations. Dielectric relaxation performance improvement strategies were further provided, in particular for the latest storage capacitors with HfO2 being implemented.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116803598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent Technology Insights on STT-MRAM: Structure, Materials, and Process Integration STT-MRAM的最新技术见解:结构、材料和工艺集成

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI: 10.1109/IMW56887.2023.10145822

Jeong-Hun Choe

引用次数: 0