Overlay Control in HAR device integration

Abstract

In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.