A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications

W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung
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Abstract

We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.
基于优化工艺的OTS-PCM存储器柱尺寸的综合研究以及用于SCM应用的低于10nm的缩放趋势
我们提出了一种用于存储类存储器(SCM)应用的相变存储器(PCM)-卵形阈值开关(OTS)存储单元的标度研究。首次在模拟支持下,实验表征了器件尺寸对OTS-PCM电池电特性的影响。实验测量和模拟结果表明,由于工艺缺陷导致器件面积缩小,OTS-PCM电池的SET阈值电压(VtS)增加。提出并实验验证了一种优化工艺,以最小化基于晶圆级表征的VtS移位问题。更重要的是,结合测量和模拟,为未来的高密度交叉点PCM (XPCM)芯片提供了器件缩小到10纳米以下的趋势。
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