Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing

Shifting computations from the central processing unit to the memory is a promising approach to lower the stress on the Von-Neumann bottleneck and to reduce the total energy consumption spend on data transfer. One promising concept for in-memory computations is the associative capacitive network introduced by Kavehei et al.. The digital information is stored in complementary resistive switches which can be read using a non-destructive read out scheme. Simulation results based on the JART VCM vlb model demonstrate the working principle of the original input encoding and the existence of capacitive sneak path currents is identified. A new input encoding is proposed in this work which not only prevents capacitive sneak paths but also improves the voltage difference between Hamming Distances (HD).