Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo
{"title":"A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation","authors":"Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo","doi":"10.1109/IMW56887.2023.10145931","DOIUrl":null,"url":null,"abstract":"Continuous shrinking of dynamic random access memory $\\langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Continuous shrinking of dynamic random access memory $\langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.
动态随机存取存储器(DRAM)特征尺寸的不断缩小不可避免地会遇到难以逾越的障碍,例如 10 纳米以下的图案化问题、超高纵横比(HAR)电容器和狭窄的传感裕度等。一个有前景的解决方案是采用三维(3D)水平堆叠晶体管和电容器的创新架构,类似于三维 NAND 架构。然而,有关三维可堆叠 DRAM 架构的工艺集成方案和电路仿真却鲜有报道。在本文中,我们首次系统地介绍了 3D DRAM 架构和集成方案。随后,我们进一步对 3D DRAM 进行了电路仿真研究,结果证实了我们提出的架构的可行性,并展示了在 DRAM 内核时序优化方面的巨大前景。