Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement

Dielectric relaxation in high-κ storage capacitors can lead to significant degradation of capacitance values and hence deteriorate read bit-error rates of DRAMs. However, the mechanism of the dielectric relaxation phenomenon in high-κ dielectric oxides and multilayer stacks is still controversial. Moreover, previous work studied the dielectric relaxation phenomenon only at high-κ film level, which lacks the necessary insights into DRAM-specific complexities and performance improvement strategies. In this work, we first set up modeling and electric testing methodologies that can reliably collect and model dielectric relaxation signal in modern DRAM high-κ capacitors at both single-cell and chip levels. Experiment and simulation evidences based on these methodologies were then presented to identify and validate charge trapping-detrapping as the physical origin of dielectric relaxation in the frequency realm of DRAM operations. Dielectric relaxation performance improvement strategies were further provided, in particular for the latest storage capacitors with HfO2 being implemented.