Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND

Abstract

In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.