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International Electron Devices Meeting 1991 [Technical Digest]最新文献

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Physics and technology of ultra short channel MOSFET devices 超短沟道MOSFET器件的物理与技术
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235433
D. Antoniadis, J. E. Chung
{"title":"Physics and technology of ultra short channel MOSFET devices","authors":"D. Antoniadis, J. E. Chung","doi":"10.1109/IEDM.1991.235433","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235433","url":null,"abstract":"It is pointed out that, as MOSFET channel lengths are scaled below about 0.15 mu m, nonstationary carrier transport effects become increasingly important. These effects can result in increased drain current over what is expected from stationary transport theory (i.e. velocity saturation), and in decreased hot-carrier energy spectrum spread, or carrier temperature, leading to improved device reliability. However, the magnitude of these effects depends strongly not only on channel length but also on overall device design such as channel doping configuration, drain junction depth, etc. Besides minimization of junction depths, optimal device design requires a super-steep-retrograde channel doping, with surface doping concentration no higher than mid-10/sup 16/ cm/sup -3/. This can be achieved with indium doping for NMOS, and antimony or arsenic doping for PMOS extreme submicron transistors.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"103 1","pages":"21-24"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78455288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Novel pseudomorphic InP/InAs/sub 0.6/P/sub 0.4/ quantum-well HEMT's 新型伪晶InP/InAs/sub 0.6/P/sub 0.4/量子阱HEMT
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235457
W. Hong, J. Hayes, R. Bhat, P. Lin, C. Nguyen, H.P. Lee, D. Yang, P. Bhattacharya
{"title":"Novel pseudomorphic InP/InAs/sub 0.6/P/sub 0.4/ quantum-well HEMT's","authors":"W. Hong, J. Hayes, R. Bhat, P. Lin, C. Nguyen, H.P. Lee, D. Yang, P. Bhattacharya","doi":"10.1109/IEDM.1991.235457","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235457","url":null,"abstract":"The authors report the first investigation of the transport properties of a 2DEG in pseudomorphic InP/InAs/sub x/P/sub 1-x/ modulation-doped heterostructures and the device characteristics of HEMTs (high electron mobility transistors) with an InP/InAs/sub 0.6/P/sub 0.4/ quantum-well channel. The dependence of the low- and high-field transport properties on the arsenic composition (x) has been studied. The Hall mobility for x=0.6 was measured to be 6100 and 52700 cm/sup 2//V-s at 300 and 77 K, respectively. The FETs having a gate length of 0.5 mu m exhibited a maximum external transconductance of 320 mS/mm and a drain saturation current density of 705 mA/mm. The f/sub T/ and f/sub max/ were measured to be 55 and 60 GHz, respectively. The saturation electron velocity was estimated to be 2.1*10/sup 7/ cm/s. The results clearly demonstrate the great potential of these material systems for high-speed applications.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"67 1","pages":"243-246"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85786042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
One dimensional electron transport and drain current quantization at 77 K in InAs heterojunction quantum wires InAs异质结量子线中77k的一维电子输运和漏极电流量子化
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235300
K. Yoh, H. Taniguchi, K. Kiyomi, M. Inoue, R. Sakamoto
{"title":"One dimensional electron transport and drain current quantization at 77 K in InAs heterojunction quantum wires","authors":"K. Yoh, H. Taniguchi, K. Kiyomi, M. Inoue, R. Sakamoto","doi":"10.1109/IEDM.1991.235300","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235300","url":null,"abstract":"The authors have fabricated quantum wires on the InAs/AlGaSb heterostructure by utilizing electron beam lithography and wet-chemical etching. The electron confinement into quasi-one-dimensional freedom of motion was verified by magnetoresistance measurement at 4.2 K. In two terminal devices with extremely narrow channel structure, quantized drain current through drain-induced barrier lowering has been observed at 77 K. Coulomb oscillations and Coulomb staircases were seen to overlap with staircase u characteristics reflecting the small parasitic capacitance between terminals. Material, structural, and temperature effects on these devices were examined.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"15 1","pages":"813-816"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87977849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electrothermal simulation tools for analysis and design of ESD protection devices (NMOSFET) 用于分析和设计ESD保护器件(NMOSFET)的电热仿真工具
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235278
K. Mayaram, J. Chern, Lawrence Arledge, Ping Yang
{"title":"Electrothermal simulation tools for analysis and design of ESD protection devices (NMOSFET)","authors":"K. Mayaram, J. Chern, Lawrence Arledge, Ping Yang","doi":"10.1109/IEDM.1991.235278","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235278","url":null,"abstract":"Two- and three-dimensional simulators have been developed to investigate the electrothermal operation of semiconductor devices and conditions for onset of thermally activated second breakdown. There are two distinct breakdown modes, one associated with a pn-junction and the other with a resistor, that can cause thermal breakdown in transistors. Simple structures have been studied for a better understanding of second breakdown. Simulations coupled with experimental results also allow the evaluation of failure thresholds of MOS devices under ESD stress conditions. It is noted that 2-D simulations are pessimistic in predicting the failure thresholds and should be used for a study of qualitative trends only.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"15 1","pages":"909-912"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91113584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs p/sup +/多晶硅双栅薄膜SOI mosfet分析
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235330
T. Tanaka, H. Horie, S. Ando, S. Hijiya
{"title":"Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs","authors":"T. Tanaka, H. Horie, S. Ando, S. Hijiya","doi":"10.1109/IEDM.1991.235330","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235330","url":null,"abstract":"The authors have fabricated planar p/sup +/ poly Si double-gate thin-film SOI (silicon-on-insulator) nMOSFETs using wafer bonding. The fabricated devices have shown a transconductance, Gm, exceeding twice that of the single-gate SOI-MOSFET. It was confirmed that conduction in the double-gate SOI MOSFET originates from a fully flat potential and charge injection. An analytical model developed by the authors has displayed electrical characteristics that agree well with those of the fabricated devices.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"11 1","pages":"683-686"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84275064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
The effect of metallic impurities on the dielectric breakdown of oxides and some new ways of avoiding them 介绍了金属杂质对氧化物介电击穿的影响及避免金属杂质的新方法
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235421
S. Verhaverbeke, M. Meuris, Paul W. Mertens, M. Heyns, A. Philipossian, D. Gräf, A. Schnegg
{"title":"The effect of metallic impurities on the dielectric breakdown of oxides and some new ways of avoiding them","authors":"S. Verhaverbeke, M. Meuris, Paul W. Mertens, M. Heyns, A. Philipossian, D. Gräf, A. Schnegg","doi":"10.1109/IEDM.1991.235421","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235421","url":null,"abstract":"The effect of metallic contamination on the dielectric breakdown of thermal oxide layers is investigated. Wafers were intentionally contaminated with Ca, Zn, Fe, Cu or Al. The oxidation behavior of the contaminants and their effect on the Si surface roughness were investigated and correlated with the oxide breakdown properties. It was observed that Ca interacts strongly with the Si substrate during ramp-up. This results in a large increase in the Si surface roughness and poor breakdown properties of the thermal oxide layer. Fe degrades the oxide integrity by the formation of defect spots during the oxidation and Al induces damage under the SiO/sub 2//poly-Si interface. Metals such as Cu and Zn diffuse easily in the Si substrate and, consequently, do not have a large impact on the oxide quality. Standard grade chemicals are the main source for the metallic impurities. After switching to ultrapure chemicals, the DI-water distribution system becomes the limiting factor. Some techniques to reduce the contamination and Si-surface roughening are presented.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"17 1","pages":"71-74"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83807266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs 采用垂直超薄SOI (DELTA) mosfet的千兆位dram的新型堆叠单元结构
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235266
D. Hisamoto, S. Kimura, T. Kaga, Y. Nakagome, M. Isoda, T. Nishida, E. Takeda
{"title":"A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs","authors":"D. Hisamoto, S. Kimura, T. Kaga, Y. Nakagome, M. Isoda, T. Nishida, E. Takeda","doi":"10.1109/IEDM.1991.235266","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235266","url":null,"abstract":"Summary form only given. The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator) MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed. Since the ultra-thin SOI structure provides high noise immunity, the storage node capacitance can be reduced by more than 50%. Therefore, in the proposed DRAM cell a large storage capacitor need not be essential, and this will extend the DRAMs miniaturization to the gigabit levels. The cell structure schematic is shown and threshold voltage dependences on channel length of DELTA-, conventional NMOS-, and PMOS-FETs are demonstrated. DELTA shows good short channel characteristics compared to conventional NMOS.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"5 1","pages":"959-961"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83858968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography 用移相光刻技术制备的0.1 μ m栅高架源极和漏极MOSFET
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235269
S. Kimura, H. Noda, D. Hisamoto, E. Takeda
{"title":"A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography","authors":"S. Kimura, H. Noda, D. Hisamoto, E. Takeda","doi":"10.1109/IEDM.1991.235269","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235269","url":null,"abstract":"Summary form only given. A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in combination with a side-wall oxide film formation technique. It is concluded that the new gate definition process utilizing phase-shifted lithography will be promising for future ultrasmall device fabrication.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"21 1","pages":"950-952"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83956164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Thermal characterization of GaAs MESFETs by means of pulsed measurements 用脉冲测量方法研究GaAs mesfet的热特性
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235454
L. Selmi, B. Riccò
{"title":"Thermal characterization of GaAs MESFETs by means of pulsed measurements","authors":"L. Selmi, B. Riccò","doi":"10.1109/IEDM.1991.235454","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235454","url":null,"abstract":"Thermal effects in GaAs MESFETs have been characterized by means of pulsed I-V measurements performed at several controlled temperatures. The temperature dependence of the main device parameters, extracted from the measured data, was implemented in a simplified, SPICE-like model of the device, coupling electrical and thermal effects. The model provides good agreement with the measured data over wide bias and temperature ranges.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"9 1","pages":"255-258"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87940924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Floating-body effect free concave SOI-MOSFETs (COSMOS) 无浮体效应的凹型soi - mosfet (COSMOS)
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235334
K. Hieda, S. Takedai, M. Takahashi, M. Yoshimi, H. Takato, A. Nitayama, F. Horiguchi
{"title":"Floating-body effect free concave SOI-MOSFETs (COSMOS)","authors":"K. Hieda, S. Takedai, M. Takahashi, M. Yoshimi, H. Takato, A. Nitayama, F. Horiguchi","doi":"10.1109/IEDM.1991.235334","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235334","url":null,"abstract":"In order to overcome the degradation induced by floating body effects and to suppress the increase in parasitic source/drain resistances in thin-film silicon-on-insulator (SOI) MOSFETs, a concave SOI-MOSFET (COSMOS) is proposed. This structure realizes a partially thin-film SOI region, which is used as a fully depleted channel, and thick-film SOI regions, which are used as source/drain. The unique features of the COSMOS are found to be (1) elimination of the floating-body effects, (2) less short channel effect, (3) excellent subthreshold characteristics, and (4) reduction in parasitic source/drain resistances.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"101 1","pages":"667-670"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77808004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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