A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography

Abstract

Summary form only given. A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in combination with a side-wall oxide film formation technique. It is concluded that the new gate definition process utilizing phase-shifted lithography will be promising for future ultrasmall device fabrication.<>