K. Nakagawa, Y. Yanagishita, N. Ishiwata, Y. Tabata
{"title":"Mask pattern designing for phase-shift lithography","authors":"K. Nakagawa, Y. Yanagishita, N. Ishiwata, Y. Tabata","doi":"10.1109/IEDM.1991.235426","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235426","url":null,"abstract":"The authors have developed a mask pattern designing algorithm for a phase-shift lithography process. This algorithm produces pattern dimension linearity regardless of the pattern size and does not requires any special CAD (computer-aided design) technique. The authors also developed a mask fabrication technique with self-aligned shifters. One can avoid the alignment problem of chromium and shifter pattern by the self-aligning mask process.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"22 1","pages":"51-54"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84387455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Klose, M. Kerber, T. Meister, M. Ohnemus, R. Kopl, P. Weger, J. Weng
{"title":"Process-optimization for sub-30 ps BiCMOS technologies for mixed ECL/CMOS applications","authors":"H. Klose, M. Kerber, T. Meister, M. Ohnemus, R. Kopl, P. Weger, J. Weng","doi":"10.1109/IEDM.1991.235417","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235417","url":null,"abstract":"The authors present a 0.8 mu m BiCMOS technology for high-performance digital applications. The underlying optimization strategy to trade off both bipolar vs. CMOS speed and cutoff-frequency vs. collector-emitter breakdown voltage is described. Based on this approach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times could be obtained for the bipolar device, making this technology perfectly suited for mixed CMOS/ECL (emitter-coupled logic) types of applications. This is additionally proved by high-speed benchmark circuits such as 2:1 frequency dividers operating up to 13.5 GHz.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"60 1","pages":"89-92"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85868322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Normal incident SiGe/Si multiple quantum well infrared detector","authors":"J. Park, R. Karunasiri, K. Wang","doi":"10.1109/IEDM.1991.235315","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235315","url":null,"abstract":"A long-wavelength ( approximately 10- mu m) quantum-well (QW) infrared detector with normal incident detection was fabricated using p-type Si/sub 1-x/Ge/sub x//Si multiple QWs. Photocurrent is measured as a function of the incident beam polarization. With a beam polarized parallel to the growth plane (90 degrees polarization, normal incidence), a photocurrent peak is observed at near 7.2 mu m with a full width at half maximum (FWHM) of about 80 meV. On the other hand, when the beam is polarized along the growth direction (0 degrees polarization), a peak is observed at near 8.6 mu m with FWHM of about 80 meV. With the non-optimized detector, the peak photoresponsivity of 0.3 A/W and detectivity of D* approximately 1.0*10/sup 9/cm square root Hz/W at 77 K are obtained for both polarizations. The results of normal incident detection demonstrate the feasibility of Si-based long-wavelength IR detectors and focal plane arrays with the advantage of monolithic integration with Si integrated circuits.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"53 1","pages":"749-752"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91250756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Norishima, H. Yoshinari, H. Hayashida, T. Eguchi, K. Kasai, H. Shinagawa, T. Matsunaga, T. Matsuno, H. Shibata, Y. Toyoshima, K. Hashimoto
{"title":"High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs","authors":"M. Norishima, H. Yoshinari, H. Hayashida, T. Eguchi, K. Kasai, H. Shinagawa, T. Matsunaga, T. Matsuno, H. Shibata, Y. Toyoshima, K. Hashimoto","doi":"10.1109/IEDM.1991.235349","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235349","url":null,"abstract":"The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"78 1","pages":"489-492"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88575299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid Boltzmann transport-Schrodinger equation model for quantum well injection transit (QWITT) diodes","authors":"K. Gullapalli, D.R. Miller, D. Neikirk","doi":"10.1109/IEDM.1991.235344","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235344","url":null,"abstract":"The authors report a self-consistent study of steady-state nonstationary transport in QWITT diodes using the pure state tunneling theory to treat transport through the double barrier quantum well region and the Boltzmann transport equation (BTE) to treat transport in the rest of the device. The distribution functions at the boundaries of the double barrier structure are evaluated, taking into account both tunneling and phonon scattering processes. It si found that velocity overshoot occurs in a region of 50 nm within the double barrier region, with a peak velocity of about 8*10/sup 7/ cm/sec occurring immediately after injection. The velocity falls rapidly to 7-8*10/sup 6/ cm/sec over a distance of 50 nm. Due to the high energy of carriers injected from the quantum well and the presence of high electric fields, the extent of the velocity overshoot in the drift region of QWITT diodes is limited.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"1 1","pages":"511-514"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91054619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel Al-Sc (scandium) alloy for future LSI interconnection","authors":"S. Ogawa, H. Nishimura","doi":"10.1109/IEDM.1991.235449","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235449","url":null,"abstract":"A new aluminum alloy, Al-Sc (scandium), has been studied in comparison with a conventional Al-Si-Cu alloy for future LSI interconnection. It has been found that Sc addition into Al completely suppressed a failure caused by a stress-induced migration phenomenon (SM) in submicron lines and hillock generation, while showing superior electromigration (EM) performance to conventional Cu addition. The new impurity, Sc, precipitates and presumably acts as a sink site for vacancies, which are the origin of the degradation in reliability by SM and EM.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"68 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90399473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.25 mu m via plug process using selective CVD aluminium for multilevel interconnection","authors":"T. Amazawa, Y. Arita","doi":"10.1109/IEDM.1991.235452","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235452","url":null,"abstract":"A multilevel interconnection with 0.25- mu m via holes has been successfully fabricated using a selective CVD (chemical vapor deposition) aluminum via plug process. Via holes on first-level aluminum interconnections have been fully plugged for the first time by selective CVD aluminum in combination with in situ RF cleaning. Specific contact resistivities of CVD aluminum via plugs are estimated to be as low as 5*10/sup -10/ Omega cm/sup 2/, and the yield for 10/sup 4/ via chains is 100% for test patterns with various via diameters of 0.25-2 mu m. Electromigration tests for the CVD aluminum plugs demonstrate extremely high reliability compared to conventional sputtering samples. The results presented demonstrate that the selective aluminum CVD process is a promising technique for future quarter-micron LSIs.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"9 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81387510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low frequency noise and quantum transport in 0.1 mu m n-MOSFETs","authors":"Z.M. Shi, J. Miéville, J. Barrier, M. Dutoit","doi":"10.1109/IEDM.1991.235378","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235378","url":null,"abstract":"Random telegraph signals (RTS) produced in deep-submicron n-MOSFETs by single electron capture and emission on oxide traps ar studied. Trap parameters, energy level, spatial location, and activation energies are derived. For temperatures lower than 20 K, the static transistor characteristics show evidence of resonant tunneling and variable range hopping mediated by localized states in the channel. When resonant tunneling dominates the transport, no RTS is measurable and a new type of low frequency current fluctuations is observed.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"267 1","pages":"363-366"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78425595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation of multiply connected current-voltage characteristics in charge injection transistors","authors":"M. Pinto, S. Luryi","doi":"10.1109/IEDM.1991.235345","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235345","url":null,"abstract":"Mappings of I-V space for charge injection transistors are obtained from device simulations. Using transport models which self-consistently incorporate electron energy and real-space transfer (RST) currents over heterostructure interfaces, multiply connected, self-intersecting I-V curves are obtained through the use of predictor-corrector continuation. These complex phase mappings help explain experimentally observed nonlinearities and suggest new regimes of device operation and application. The analysis suggests that the loops and folds in I-V space, which cannot be continuously traced in measurements (or conventional simulations), are responsible for the nonlinear steps observed after the onset of RST in experiments. These results can be reproduced qualitatively by any transport model which incorporates RST self-consistently.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"20 1","pages":"507-510"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82554726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Combined reactor, wafer, and feature scale simulation of selective silicon epitaxial growth","authors":"T.-K. Yu, S. Park, J. Fitch, M. Orłowski","doi":"10.1109/IEDM.1991.235285","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235285","url":null,"abstract":"A combined approach to the modeling of selective epitaxial silicon growth (SEG) is presented. The simulations consider the following effects: reactor fluid dynamics, gas chemistry, mass transport in the stagnant layer, and device profile evolution. Reactor-scale, wafer-scale and feature-scale simulations are used to model these mechanisms which have a wide range of physical dimensions. Experiments to identify the effects of HCl on silicon growth rates have been performed. The experimental results show that the main effect of HCl is modulation of reactant gas composition, and they provide the rate constants necessary to simulate local loading effects in the stagnant layer simulation.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"1 1","pages":"879-882"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83844634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}