M. Norishima, H. Yoshinari, H. Hayashida, T. Eguchi, K. Kasai, H. Shinagawa, T. Matsunaga, T. Matsuno, H. Shibata, Y. Toyoshima, K. Hashimoto
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引用次数: 3
摘要
提出了一种用于嵌入式大容量ram(静态ram)、供电电压为3.3 V的逻辑lsi的0.5 μ m CMOS的最佳器件设计。为了在3.3 V电源下获得优异的性能，设计了p-MOSFET结构，并对栅极氧化物厚度和结电容进行了优化。实现了p衬底上三孔结构的多晶硅负载SRAM电池，采用wsi多晶硅栅极电极，并采用W插头过孔进行三能级金属化。通过对各个参数的精心设计和技术的合理集成，实现了具有大容量高速缓存存储器的高性能0.5 μ m CMOS。
High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs
The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized.<>
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