用于混合ECL/CMOS应用的低于30 ps BiCMOS技术的工艺优化

International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI:10.1109/IEDM.1991.235417

H. Klose, M. Kerber, T. Meister, M. Ohnemus, R. Kopl, P. Weger, J. Weng

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引用次数: 10

摘要

作者提出了一种用于高性能数字应用的0.8 μ m BiCMOS技术。描述了平衡双极与CMOS速度和截止频率与集电极-发射极击穿电压的潜在优化策略。基于这种方法，双极器件可以获得23.5 GHz截止频率和28 ps CML门延迟时间，使该技术非常适合混合CMOS/ECL(发射器耦合逻辑)类型的应用。高速基准电路(如工作频率高达13.5 GHz的2:1分频器)也证明了这一点

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Process-optimization for sub-30 ps BiCMOS technologies for mixed ECL/CMOS applications

The authors present a 0.8 mu m BiCMOS technology for high-performance digital applications. The underlying optimization strategy to trade off both bipolar vs. CMOS speed and cutoff-frequency vs. collector-emitter breakdown voltage is described. Based on this approach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times could be obtained for the bipolar device, making this technology perfectly suited for mixed CMOS/ECL (emitter-coupled logic) types of applications. This is additionally proved by high-speed benchmark circuits such as 2:1 frequency dividers operating up to 13.5 GHz.<>

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International Electron Devices Meeting 1991 [Technical Digest]

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