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Proceedings of International Electron Devices Meeting最新文献

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Low-noise 650 nm-band AlGaInP visible lasers with highly-doped saturable absorbing (HDSA) layer 具有高掺杂饱和吸收(HDSA)层的低噪声650nm波段AlGaInP可见光激光器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499284
Kidoguchi, I. Adachi, S. Kamiyama, T. Fukuhisa, P. Mannoh, A. Takamori, T. Uenoyama
{"title":"Low-noise 650 nm-band AlGaInP visible lasers with highly-doped saturable absorbing (HDSA) layer","authors":"Kidoguchi, I. Adachi, S. Kamiyama, T. Fukuhisa, P. Mannoh, A. Takamori, T. Uenoyama","doi":"10.1109/IEDM.1995.499284","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499284","url":null,"abstract":"Self-sustained pulsating 650 nm-band AlGaInP visible laser diodes were successfully demonstrated by adopting novel structure, which has highly doped saturable absorbing layer. Short carrier lifetime, which is indispensable for pulsation, was realized by applying high doping concentration to the saturable absorbing layer. 500 /spl mu/m-long devices with 51%/51% coated facets were fabricated, resulting in the threshold current of 65 mA at room temperature. The relative intensity noise was below -134 dB/Hz in the temperature ranging from 20 to 60/spl deg/C at 5 mW.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The fabrication and characterization of large scale integrated field emitter arrays for high current electron sources 大电流电子源大规模集成场发射阵列的制造与表征
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499387
M. Urayama, T. Tokumaru, Y. Takegawa, Y. Morita, Y. Maruo, T. Ide, Y. Inoue, S. Yano
{"title":"The fabrication and characterization of large scale integrated field emitter arrays for high current electron sources","authors":"M. Urayama, T. Tokumaru, Y. Takegawa, Y. Morita, Y. Maruo, T. Ide, Y. Inoue, S. Yano","doi":"10.1109/IEDM.1995.499387","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499387","url":null,"abstract":"We report on the fabrication and the characteristics of large scale integrated field emitter arrays (FEAs) containing six million emitters. Our FEAs have a unique structure having a thermal-oxidized SiO/sub 2/ film as an insulator layer which separates the gate electrodes from the silicon cathode substrate. An anode current of 63.8 mA at 58.7 V has been obtained in the six million field emitters. This is one of the highest values reported in the world to date. From the FEA characteristics we have estimated a variation of the radius of curvature of the emitter tips. This variation has been found to be within 6.4 nm /spl plusmn/1.05 nm.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Volcano-shaped field emitters for large area displays 用于大面积显示的火山状场发射器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499225
H. Busta, G. Gammie, S. Skala, J. Pogemiller, R. Nowicki, J. Hubacek, D. Devine, R. Rao, W. Urbanek
{"title":"Volcano-shaped field emitters for large area displays","authors":"H. Busta, G. Gammie, S. Skala, J. Pogemiller, R. Nowicki, J. Hubacek, D. Devine, R. Rao, W. Urbanek","doi":"10.1109/IEDM.1995.499225","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499225","url":null,"abstract":"Individual and groups of 3/spl times/3 and 10/spl times/10 gated volcano-shaped field emitters have been processed with gate dimensions of 4, 8, 14, 25 and 50 /spl mu/m and gate-to-emitter rim distances of 1.0 and 0.25 /spl mu/m. The 0.25 /spl mu/m devices are fabricated with a stepped oxide process which does not increase the gate-to-emitter capacitance significantly. Turn-on voltages range from 80-90 V for the 0.25 /spl mu/m devices and are about 250 V for the 1.0 /spl mu/m devices. I-V characteristics will be presented as well as an integration scheme for the formation of matrix-addressable arrays for field emitter display (FED) applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132514901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Device drive current degradation observed with retrograde channel profiles 用逆行通道剖面观察到的器件驱动电流退化
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499228
S. Venkatesan, J. Lutze, C. Lage, W. Taylor
{"title":"Device drive current degradation observed with retrograde channel profiles","authors":"S. Venkatesan, J. Lutze, C. Lage, W. Taylor","doi":"10.1109/IEDM.1995.499228","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499228","url":null,"abstract":"Super steep retrograde channel profiles have been widely known to produce improved short channel characteristics in sub-0.35 /spl mu/m CMOS technologies. In this paper, an attempt is made to leverage this improved short channel behaviour and thereby improve transistor performance (as measured by the current drive). Whereas significant improvements in short channel effects measured by DIBL and /spl Delta/Vt/sub sat/ are obtained with retrograde channels, it is observed that for a fixed gate length and equal threshold voltage, transistors with retrograde channel profiles typically exhibit lower drive currents than equivalent transistors fabricated with conventional doping profiles. Potential trade offs in device design resulting from this observation are discussed.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131634303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Performance and reliability concerns of ultra-thin SOI and ultra-thin gate oxide MOSFETs 超薄SOI和超薄栅氧化mosfet的性能和可靠性问题
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499349
A. Toriumi, J. Koga, H. Satake, A. Ohata
{"title":"Performance and reliability concerns of ultra-thin SOI and ultra-thin gate oxide MOSFETs","authors":"A. Toriumi, J. Koga, H. Satake, A. Ohata","doi":"10.1109/IEDM.1995.499349","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499349","url":null,"abstract":"Inversion layer mobility in thin SOI MOSFETs has been investigated from the viewpoint of the SOI thickness effects on device performance. Next, thin oxide properties such as Qbd, Vgt, Dit, and SILC have been studied as a function of oxide thickness. It is demonstrated that there is a small window for high reliability in ultra-thin SiO/sup 2/ regime.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
An mK/spl times/nK modular image sensor design 一种mK/spl倍/nK模块化图像传感器设计
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497203
G. Kreider, J. Bosiers, B. Dillen, J. van der Heijden, W. Hoekstra, A. Kleimann, P. Opmeer, J. Oppers, H. Peek, R. Pellens, A. Theuwissen
{"title":"An mK/spl times/nK modular image sensor design","authors":"G. Kreider, J. Bosiers, B. Dillen, J. van der Heijden, W. Hoekstra, A. Kleimann, P. Opmeer, J. Oppers, H. Peek, R. Pellens, A. Theuwissen","doi":"10.1109/IEDM.1995.497203","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497203","url":null,"abstract":"A 1 K/spl times/2 K full frame sensor demonstrates a new modular sensor design. Each imager in the family is built from smaller, abutable blocks which are exposed in the correct position during lithography. These blocks can be stacked to form sensors of arbitrary size, all based on the same pixel structure. These pixels have a high charge handling capability, vertical anti-blooming, electronic shuttering, a high light sensitivity, and low dark current.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133238293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An effective cross-talk isolation structure for power IC applications 一种用于功率集成电路应用的有效串扰隔离结构
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499378
Wilson W. S. Chan, J. Sin, S.S. Wong
{"title":"An effective cross-talk isolation structure for power IC applications","authors":"Wilson W. S. Chan, J. Sin, S.S. Wong","doi":"10.1109/IEDM.1995.499378","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499378","url":null,"abstract":"The simple and effective cross-talk isolation structure consists of an isolator and a collector, and is placed in the epitaxial layer between the CMOS structure and the power device. Results show that, with the use of the isolation structure, operating current of the body diode of the LDMOST can be improved by 16 times and operating current of the LIGBT can be improved by 5 times before CMOS latchup in the control circuit occurs. For dynamic interaction between integrated LIGBTs, 8 times reduction in current surge in the adjacent device during turn-off transient is observed.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132935127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
In situ CMP monitoring technique for multi-layer interconnection 多层互连的原位CMP监测技术
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499240
A. Fukuroda, K. Nakamura, Y. Arimoto
{"title":"In situ CMP monitoring technique for multi-layer interconnection","authors":"A. Fukuroda, K. Nakamura, Y. Arimoto","doi":"10.1109/IEDM.1995.499240","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499240","url":null,"abstract":"An all-around in situ monitor for CMP was developed. It can detect the even surface during planarization, polishing pad wear, lack of uniformity on the surface of a wafer, and the interface of different materials. In this method, small vibrations of the polishing head were detected by using an accelerometer, and signal processing techniques were used to determine polishing events.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133803491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A scaled 1.8 V, 0.18 /spl mu/m gate length CMOS technology: device design and reliability considerations 一种缩放1.8 V, 0.18 /spl mu/m栅极长度的CMOS技术:器件设计和可靠性考虑
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499227
M. Rodder, S. Aur, I. Chen
{"title":"A scaled 1.8 V, 0.18 /spl mu/m gate length CMOS technology: device design and reliability considerations","authors":"M. Rodder, S. Aur, I. Chen","doi":"10.1109/IEDM.1995.499227","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499227","url":null,"abstract":"Device design improvements for scaling to a high performance 1.8 V, 0.18 /spl mu/m gate length CMOS technology are presented. nMOS with nominal I/sub drive/(I/sub drive//sup nom/)=55 /spl mu/A//spl mu/m drive (with t/sub ox//sup acc/=43 /spl Aring/, t/sub ox//sup inv/=49 /spl Aring/ from C-V at V/sub gb/=-4, +2.5V), R/sub sd/<280 /spl Omega/-/spl mu/m, L/sub g//sup min/ (minimum gate length at I/sub off/=1 nA//spl mu/m)=0.16 /spl mu/m, and hot carrier lifetime /spl Gt/10 years is achieved. Increased As HDD dose, pocket implant, and RTA HDD anneal are required for simultaneous high I/sub drive//sup nom/, high carrier velocity vs. DIBL, and L/sub g//sup min/=0.16 /spl mu/m. pMOS with L/sub g//sup min/=0.16 /spl mu/m and with I/sub drive//sup nom/=220 /spl mu//spl alpha///spl mu/m is achieved. BF/sub 2/ HDD plus RTA HDD anneal prior to sidewall deposition to eliminate interstitial enhanced B tail diffusion are utilized to form more abrupt pMOS HDD junctions. Super-steep retrograde (SSR) As channel profile reduces SCE and increases v/sub eff/ (and I/sub drive/) vs. DIBL, but decreases v/sub eff/ (and I/sub drive/) vs. I/sub off/, compared to a non-SSR profile. pMOS (I/sub drive//sup nom/)=220 /spl mu/A//spl mu/m (with non-SSR profile) and nMOS I/sub drive//sup nom/)=550 /spl mu/A//spl mu/m result in a 30% improvement in speed for the 1.8 V, 0.18 /spl mu/m technology compared to a prior 2.5 V, 0.25 /spl mu/m technology.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122391386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A novel LDMOS structure with a step gate oxide 一种新型阶梯栅氧化物结构的LDMOS
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499376
D. Lin, S. Tu, Y. See, P. Tam
{"title":"A novel LDMOS structure with a step gate oxide","authors":"D. Lin, S. Tu, Y. See, P. Tam","doi":"10.1109/IEDM.1995.499376","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499376","url":null,"abstract":"High performance power device is essential for power integrated circuits and discrete power devices. A novel LDMOS structure with step gate oxide is proposed for breakdown voltage or on state resistance (Ron) improvement. The step gate oxide is introduced on the LDMOS's drift region. The thicker step gate oxide can improve device breakdown voltage without significantly affecting other device electric parameters. As a result, drain can be pulled back and self-aligned to the gate. This can significantly reduce device drift region and improves device on state resistance. This approach is different from conventional approach (with or without field oxide on the drain side) which drain is not self-aligned to the gate.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123013251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
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