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Proceedings of International Electron Devices Meeting最新文献

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Re-examination of indium implantation for a low power 0.1 /spl mu/m technology 低功率0.1 /spl mu/m技术的铟注入再检验
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499361
P. Bouillon, F. Benistant, T. Skotnicki, G. Guégan, D. Roche, E. André, D. Mathiot, S. Tedesco, F. Martin, M. Heitzmann, M. Lerme, M. Haond
{"title":"Re-examination of indium implantation for a low power 0.1 /spl mu/m technology","authors":"P. Bouillon, F. Benistant, T. Skotnicki, G. Guégan, D. Roche, E. André, D. Mathiot, S. Tedesco, F. Martin, M. Heitzmann, M. Lerme, M. Haond","doi":"10.1109/IEDM.1995.499361","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499361","url":null,"abstract":"The use of indium for NMOS channel doping in a 0.1 /spl mu/m CMOS technology is fully re-considered. For the first time, we clearly demonstrate that the room temperature carrier freeze-out is responsible for large discrepancies between spreading resistance and SIMS measurements but that it does not affect Indium doped NMOSFET's operation. 0.1 /spl mu/m NMOS transistors have been fabricated using Indium for channel doping. A strong reduction in short channel effect and a slight improvement in the effective low-field mobility have been obtained.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Monolithic 26 GHz and 40 GHz VCOs with SiGe heterojunction bipolar transistor 单片26ghz和40ghz压控振荡器与SiGe异质结双极晶体管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499321
A. Gruhle, A. Schuppen, U. Konig, U. Erben, H. Schumacher
{"title":"Monolithic 26 GHz and 40 GHz VCOs with SiGe heterojunction bipolar transistor","authors":"A. Gruhle, A. Schuppen, U. Konig, U. Erben, H. Schumacher","doi":"10.1109/IEDM.1995.499321","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499321","url":null,"abstract":"Monolithically integrated 26 GHz and 40 GHz VCOs have been built with SiGe heterojunction bipolar transistors (HBT). The tuning range was more than 3 GHz, the output power behind an on-chip 10 dB-attenuator reached -13 dBm. The HBTs and the varactors were fabricated on the same high-resistivity substrate using the same MBE-grown layers. The transistors had an f/sub max/ of about 60 GHz and were operated in common-emitter series feedback configuration. Chip sizes including the microstrip resonators were 2/spl times/2.8 mm/sup 2/.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
"NET-AN" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications “NET-AN”是一个全三维寄生互连分布式RLC提取器，适用于大型全芯片应用
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499246
O. Akcasu, J. Lu, A. Dalal, S. Mitra, L. Lev, N. Vassegihi, A. Pance, H. Hingarh, H. Basit
{"title":"\"NET-AN\" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications","authors":"O. Akcasu, J. Lu, A. Dalal, S. Mitra, L. Lev, N. Vassegihi, A. Pance, H. Hingarh, H. Basit","doi":"10.1109/IEDM.1995.499246","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499246","url":null,"abstract":"A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122812581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides 超薄氧化物中本征击穿厚度依赖的一致模型
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499353
R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, H. Maes
{"title":"A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides","authors":"R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, H. Maes","doi":"10.1109/IEDM.1995.499353","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499353","url":null,"abstract":"A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes wearout as a hole induced generation of electron traps. Breakdown is defined as conduction via these traps from one interface to the other. Implementing the model in a simulator, the oxide thickness dependence of the Weibull slope of the Q/sub BD/-distribution is predicted, and, using the unique relationship between hole fluence and generated electron trap density, the decrease of the critical hole fluence with oxide thickness is explained.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 317
Effects of scaling thickness and niobium doping level on ferroelectric thin film capacitor memory operation 结垢厚度和铌掺杂水平对铁电薄膜电容器记忆性能的影响
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497197
Francis K. Chai, peixiong zhao, J. Brews, D. Birnie, K. Galloway, R. Vogt, M. Orr
{"title":"Effects of scaling thickness and niobium doping level on ferroelectric thin film capacitor memory operation","authors":"Francis K. Chai, peixiong zhao, J. Brews, D. Birnie, K. Galloway, R. Vogt, M. Orr","doi":"10.1109/IEDM.1995.497197","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497197","url":null,"abstract":"Ferroelectric thin film capacitors (FTFCs) are the basic storage element in ferroelectric memory cells. In this paper, the effects of varying film thickness and niobium doping level on electrical properties for memory applications in FTFCs are examined. Reliability issues such as leakage current and fatigue are studied while the niobium doping level is varied. We find that reducing film thickness (in 0.3 /spl mu/m range) by a factor of 2 should be accompanied by addition of niobium doping up to 5% in order to maintain reliable capacitor operation.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121956163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High power AlGaAs/GaAs HBTs and their application to mobile communications systems 高功率AlGaAs/GaAs hbt及其在移动通信系统中的应用
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499335
T. Yoshimasu
{"title":"High power AlGaAs/GaAs HBTs and their application to mobile communications systems","authors":"T. Yoshimasu","doi":"10.1109/IEDM.1995.499335","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499335","url":null,"abstract":"This paper addresses the power application of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) to L-band mobile communications systems. From points of view of circuit and systems design, features of HBT technology are discussed and compared with those of GaAs MESFET technology.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121958756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Characteristics of the PZT thin film device fabricated on the single grain 单晶PZT薄膜器件的特性
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497198
J. Joo, S. Joo
{"title":"Characteristics of the PZT thin film device fabricated on the single grain","authors":"J. Joo, S. Joo","doi":"10.1109/IEDM.1995.497198","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497198","url":null,"abstract":"It was found that when tantalum was added to PZT (PbZr/sub x/Ti/sub 1-x/O/sub 3/), the grain size of the sputter-deposited PZT films could be significantly enlarged so that abnormally large single grains could be obtained through so called SRCC (Selective Radiation Controlled Crystallization) process. Electrical measurements of the single grained PZT thin films strongly indicated that the current problems with the polycrystalline PZT thin films such as high leakage current, low breakdown field, fatigue and aging can be solved. The single grained PZT films showed low leakage current (J/sub LC//spl sim/1/spl times/10/sup -8/ A/cm/sup 2/) and excellent polarization properties (Q/sub c//spl sim/35 /spl mu/C/cm/sup 2/, Pr/spl sim/15 /spl mu/C/cm/sup 2/).","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116023510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell 利用带对带隧道诱导热电子(BBHE)注入p通道快闪存储器的新方法
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499196
T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, H. Miyoshi
{"title":"Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell","authors":"T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, H. Miyoshi","doi":"10.1109/IEDM.1995.499196","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499196","url":null,"abstract":"A novel electron injection scheme for flash memory is proposed, where band-to-band tunneling induced hot electrons (BBHE) are employed in a P-channel cell. This proposed method ensures the realization of high program efficiency, high scalability and hot-hole-injection-free operation. We also demonstrate an application of the method to DINOR (DIvided bit-line NOR) program operation. An ultra-high-speed programming of 60 nsec/Byte can be achieved with a leakage current less than 1 mA by utilizing 512 Byte parallel programming. This new DINOR flash memory is shown to be the most promising for the realization of a low-voltage, high-performance and high-reliability flash memory of 64 Mbits and beyond.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
TFSOI CMOS technology for sub-1 V microcontroller circuits 用于sub- 1v微控制器电路的TFSOI CMOS技术
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497182
W.M. Huang, K. Papworth, M. Racanelli, J. John, J. Foerstner, H. Shin, H. Park, B. Hwang, T. Wetteroth, S. Hong, H. Shin, S. Wilson, S. Cheng
{"title":"TFSOI CMOS technology for sub-1 V microcontroller circuits","authors":"W.M. Huang, K. Papworth, M. Racanelli, J. John, J. Foerstner, H. Shin, H. Park, B. Hwang, T. Wetteroth, S. Hong, H. Shin, S. Wilson, S. Cheng","doi":"10.1109/IEDM.1995.497182","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497182","url":null,"abstract":"For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 /spl mu/m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than the SRAM and ROM circuits. The stress-induced leakage also causes abnormal frequency vs. V/sub DD/ behavior with the CPU. CPU yield comparable to bulk CMOS, combined with a /spl sim/2/spl times/ maximum clock frequency enhancement, is achieved with the optimized low-leakage TFSOI process.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122360418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Bipolar installed CMOS technology without any process step increase for high speed cache SRAM 双极安装CMOS技术，没有任何工艺步骤增加高速缓存SRAM
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499309
K. Ishimaru, M. Takahashi, M. Nishigohori, Y. Okayama, Y. Unno, F. Matsuoka, M. Kakumu
{"title":"Bipolar installed CMOS technology without any process step increase for high speed cache SRAM","authors":"K. Ishimaru, M. Takahashi, M. Nishigohori, Y. Okayama, Y. Unno, F. Matsuoka, M. Kakumu","doi":"10.1109/IEDM.1995.499309","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499309","url":null,"abstract":"Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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