"NET-AN" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications

Abstract

A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts.