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A hot-carrier triggered SCR for smart power bus ESD protection 用于智能电源母线ESD保护的热载波触发可控硅
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499210
J. Watt, A. Walker
{"title":"A hot-carrier triggered SCR for smart power bus ESD protection","authors":"J. Watt, A. Walker","doi":"10.1109/IEDM.1995.499210","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499210","url":null,"abstract":"A hot-carrier triggered SCR (HCTSCR) has been developed for power bus electrostatic discharge (ESD) protection. Substrate current generated by hot electrons in an n-channel FET is used to latch an SCR structure connected between the power buses during an ESD event. A trigger circuit is used to control the hot-carrier generation such that the turn-on voltage of the HCTSCR is reduced during the fast voltage ramp characteristic of ESD. The turn-on voltage of the HCTSCR can be accurately tuned by adjusting the gate length of the trigger FET. The HCTSCR has been implemented in a 0.5 /spl mu/m CMOS SRAM technology and has been demonstrated to provide protection against HBM ESD in excess of 8800 V without any degradation in latch-up.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115718484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography 采用x射线光刻技术的新型简单Ru/(Ba,Sr)TiO/sub 3//Ru堆叠电容器的千兆比特规模DRAM单元
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499362
Y. Nishioka, K. Shiozawa, T. Oishi, K. Kanamoto, Y. Tokuda, H. Sumitani, S. Aya, H. Yabe, K. Itoga, T. Hifumi, K. Marumoto, T. Kuroiwa, T. Kawahara, K. Nishikawa, T. Oomori, T. Fujino, S. Yamamoto, S. Uzawa, M. Kimata, M. Nunoshita, H. Abe
{"title":"Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography","authors":"Y. Nishioka, K. Shiozawa, T. Oishi, K. Kanamoto, Y. Tokuda, H. Sumitani, S. Aya, H. Yabe, K. Itoga, T. Hifumi, K. Marumoto, T. Kuroiwa, T. Kawahara, K. Nishikawa, T. Oomori, T. Fujino, S. Yamamoto, S. Uzawa, M. Kimata, M. Nunoshita, H. Abe","doi":"10.1109/IEDM.1995.499362","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499362","url":null,"abstract":"We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell with 0.14-/spl mu/m process technology, which is promising for 1-gigabit DRAMs and beyond. We developed three advanced technologies for this fabrication. Firstly, synchrotron radiation (SR) X-ray lithography was used to replicate ultra-fine patterns instead of optical lithography. Secondly, we introduced a simple stacked capacitor composed of a metal-organic chemical vapor deposition (MOCVD) grown (Ba,Sr)TiO/sub 3/ (BST) high-dielectric-constant film sandwiched by Ru-metal electrodes. Thirdly, we developed advanced etching techniques for the fine pattern fabrication using improved ECR discharged plasmas, which give less microloading effects.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127352001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Resonant-cavity photodetectors 共振腔光电探测器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499287
J. Campbell
{"title":"Resonant-cavity photodetectors","authors":"J. Campbell","doi":"10.1109/IEDM.1995.499287","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499287","url":null,"abstract":"The rapid emergence of high-performance optical systems has accentuated the need for photodiodes with enhanced performance and functionality. In this paper we will describe a new class of photodiodes that utilize novel resonant-cavity structures to achieve high speed, high quantum efficiency, and a narrow spectral response that may prove useful for some wavelength division multiplexing applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125100896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
100 mW high-power angled-stripe superluminescent diodes with a new real refractive index guided self-aligned structure 一种新型真实折射率引导自对准结构的100mw大功率角条纹超发光二极管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499285
T. Takayama, C. Imafuji, Y. Kouchi, M. Yuri, M. Kume, A. Yoshikawa, M. Itoh
{"title":"100 mW high-power angled-stripe superluminescent diodes with a new real refractive index guided self-aligned structure","authors":"T. Takayama, C. Imafuji, Y. Kouchi, M. Yuri, M. Kume, A. Yoshikawa, M. Itoh","doi":"10.1109/IEDM.1995.499285","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499285","url":null,"abstract":"We have developed for the first time 100 mW high-power angled-stripe superluminescent diodes with a new real refractive index guided self-aligned structure. The structure has a GaAlAs optical confinement layer on a planar active layer and an inclined current injection stripe by 5/spl deg/ with respect to the facets. That gives small internal loss (/spl sim/10 cm/sup -1/) and facet power reflectivity less than the order of 10/sup -6/. As a result, the output power as high as 105 mW at a low operating current of 270 mA is obtained with less than 3% spectral modulation and 10.5 nm full width at half maximum spectral width.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A sputter equipment simulation system including molecular dynamical target atom scattering model 一种包含分子动力学靶原子散射模型的溅射设备仿真系统
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497190
H. Yamada, T. Shinmura, T. Ohta
{"title":"A sputter equipment simulation system including molecular dynamical target atom scattering model","authors":"H. Yamada, T. Shinmura, T. Ohta","doi":"10.1109/IEDM.1995.497190","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497190","url":null,"abstract":"We have developed an advanced sputter equipment simulation system to design the deposition equipment for ULSI with high aspect ratios contact holes. The system is composed of a newly developed target atom scattering model and die profile model with the Monte Carlo (MC) method. The target atom scattering model uses the Molecular Dynamics (MD) technique combined with thermal analysis and derives ejection angle distribution. The simulated results of titanium (Ti) bottom coverage vs. applied voltage agree with experiments within 10% accuracy.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A PN gate polysilicon thin film transistor 一种PN栅多晶硅薄膜晶体管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499346
B. Min, Cheol‐Min Park, M. Han
{"title":"A PN gate polysilicon thin film transistor","authors":"B. Min, Cheol‐Min Park, M. Han","doi":"10.1109/IEDM.1995.499346","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499346","url":null,"abstract":"We propose and fabricate a new polysilicon thin film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a non-offset structure in the ON state. The fabrication process is compatible with the conventional non-offset poly-Si TFTs process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the non-offset device, while the ON current of the new device is almost identical with that of the non-offset device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"65 2 Spec No 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126770750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Volatile and non-volatile memories in silicon with nano-crystal storage 具有纳米晶体存储的易失性和非易失性硅存储器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499252
S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan
{"title":"Volatile and non-volatile memories in silicon with nano-crystal storage","authors":"S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan","doi":"10.1109/IEDM.1995.499252","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499252","url":null,"abstract":"A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 200
Multi-level flash/EPROM memories: new self-convergent programming methods for low-voltage applications 多电平闪存/EPROM存储器:低压应用的新自收敛编程方法
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499194
M. Chi, A. Bergemont
{"title":"Multi-level flash/EPROM memories: new self-convergent programming methods for low-voltage applications","authors":"M. Chi, A. Bergemont","doi":"10.1109/IEDM.1995.499194","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499194","url":null,"abstract":"This paper proposes new low voltage programming methods for storing multi-levels of threshold voltage (V/sub T/) in flash memory cells. These methods are based on hot electron injection under low voltage (<5v) bias at drain or gate. Abundant hot electrons can be generated from the high field near drain together with various \"seed\" currents for avalanche mechanism, such as punch-through and parasitic bipolar currents in cell. The programmed cell V/sub T/ has excellent linear relation to the gate bias used for programming, therefore this technique is also useful for storing analog signals in cells. Many array architectures, such as NVG or ETOX, can be implemented with capability of programming one or more entire columns of cells into multi-levels or analog signals simultaneously. The methods demonstrated in this paper are promising for next generation high density and low power flash memory with applications in both digital and analog systems.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121999171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs 一种基于ECR MOCVD (Ba,Sr)TiO/sub 3/堆叠电容技术，具有RuO/sub 2//Ru/TiN/TiSi/sub x/存储节点
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497196
S. Yamamichi, P. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, H. Ono
{"title":"An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs","authors":"S. Yamamichi, P. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, H. Ono","doi":"10.1109/IEDM.1995.497196","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497196","url":null,"abstract":"A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116823866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs 采用各向异性选择性外延硅的自对准触点技术用于千兆位dram
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499307
H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, K. Koyama
{"title":"A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs","authors":"H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, K. Koyama","doi":"10.1109/IEDM.1995.499307","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499307","url":null,"abstract":"A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700/spl deg/C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 /spl mu/m/sup 2/ with a 0.20 /spl mu/m design rule can be achieved.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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