H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, K. Koyama
{"title":"采用各向异性选择性外延硅的自对准触点技术用于千兆位dram","authors":"H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, K. Koyama","doi":"10.1109/IEDM.1995.499307","DOIUrl":null,"url":null,"abstract":"A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700/spl deg/C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 /spl mu/m/sup 2/ with a 0.20 /spl mu/m design rule can be achieved.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs\",\"authors\":\"H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, K. Koyama\",\"doi\":\"10.1109/IEDM.1995.499307\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700/spl deg/C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 /spl mu/m/sup 2/ with a 0.20 /spl mu/m design rule can be achieved.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499307\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499307","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs
A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700/spl deg/C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 /spl mu/m/sup 2/ with a 0.20 /spl mu/m design rule can be achieved.
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