S. Yamamichi, P. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, H. Ono
{"title":"一种基于ECR MOCVD (Ba,Sr)TiO/sub 3/堆叠电容技术，具有RuO/sub 2//Ru/TiN/TiSi/sub x/存储节点","authors":"S. Yamamichi, P. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, H. Ono","doi":"10.1109/IEDM.1995.497196","DOIUrl":null,"url":null,"abstract":"A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs\",\"authors\":\"S. Yamamichi, P. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, H. Ono\",\"doi\":\"10.1109/IEDM.1995.497196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.497196\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.497196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs
A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.
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