Y. Nishioka, K. Shiozawa, T. Oishi, K. Kanamoto, Y. Tokuda, H. Sumitani, S. Aya, H. Yabe, K. Itoga, T. Hifumi, K. Marumoto, T. Kuroiwa, T. Kawahara, K. Nishikawa, T. Oomori, T. Fujino, S. Yamamoto, S. Uzawa, M. Kimata, M. Nunoshita, H. Abe
{"title":"Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography","authors":"Y. Nishioka, K. Shiozawa, T. Oishi, K. Kanamoto, Y. Tokuda, H. Sumitani, S. Aya, H. Yabe, K. Itoga, T. Hifumi, K. Marumoto, T. Kuroiwa, T. Kawahara, K. Nishikawa, T. Oomori, T. Fujino, S. Yamamoto, S. Uzawa, M. Kimata, M. Nunoshita, H. Abe","doi":"10.1109/IEDM.1995.499362","DOIUrl":null,"url":null,"abstract":"We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell with 0.14-/spl mu/m process technology, which is promising for 1-gigabit DRAMs and beyond. We developed three advanced technologies for this fabrication. Firstly, synchrotron radiation (SR) X-ray lithography was used to replicate ultra-fine patterns instead of optical lithography. Secondly, we introduced a simple stacked capacitor composed of a metal-organic chemical vapor deposition (MOCVD) grown (Ba,Sr)TiO/sub 3/ (BST) high-dielectric-constant film sandwiched by Ru-metal electrodes. Thirdly, we developed advanced etching techniques for the fine pattern fabrication using improved ECR discharged plasmas, which give less microloading effects.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell with 0.14-/spl mu/m process technology, which is promising for 1-gigabit DRAMs and beyond. We developed three advanced technologies for this fabrication. Firstly, synchrotron radiation (SR) X-ray lithography was used to replicate ultra-fine patterns instead of optical lithography. Secondly, we introduced a simple stacked capacitor composed of a metal-organic chemical vapor deposition (MOCVD) grown (Ba,Sr)TiO/sub 3/ (BST) high-dielectric-constant film sandwiched by Ru-metal electrodes. Thirdly, we developed advanced etching techniques for the fine pattern fabrication using improved ECR discharged plasmas, which give less microloading effects.
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