A hot-carrier triggered SCR for smart power bus ESD protection

Abstract

A hot-carrier triggered SCR (HCTSCR) has been developed for power bus electrostatic discharge (ESD) protection. Substrate current generated by hot electrons in an n-channel FET is used to latch an SCR structure connected between the power buses during an ESD event. A trigger circuit is used to control the hot-carrier generation such that the turn-on voltage of the HCTSCR is reduced during the fast voltage ramp characteristic of ESD. The turn-on voltage of the HCTSCR can be accurately tuned by adjusting the gate length of the trigger FET. The HCTSCR has been implemented in a 0.5 /spl mu/m CMOS SRAM technology and has been demonstrated to provide protection against HBM ESD in excess of 8800 V without any degradation in latch-up.