A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs

Abstract

A self-aligned contact pad formation technology for giga-bit DRAMs has been developed using anisotropical selective epitaxial silicon grown at 700/spl deg/C. Interfacial contact resistance was reduced to approximately one-fifth of that of a conventional poly-Si plugged contact. The smallest memory cell size of 0.24 /spl mu/m/sup 2/ with a 0.20 /spl mu/m design rule can be achieved.