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Proceedings of International Electron Devices Meeting最新文献

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A front gate charge pumping technique for measuring both interfaces in fully depleted SOI/MOSFETs 一种用于测量完全耗尽SOI/ mosfet中两个界面的前门电荷泵送技术
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499302
Yujun Li, Guobin Wang, T. Ma
{"title":"A front gate charge pumping technique for measuring both interfaces in fully depleted SOI/MOSFETs","authors":"Yujun Li, Guobin Wang, T. Ma","doi":"10.1109/IEDM.1995.499302","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499302","url":null,"abstract":"A simple front-gate charge pumping technique has been developed, which enables the measurement of interface traps at both the front and the back interfaces of a fully depleted SOI/MOSFET. It is based on the strong coupling between the two interfaces, and its validity has been verified both experimentally and by computer simulation.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124992287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A neuron MOS transistor-based multiplier cell 基于神经元MOS晶体管的乘法器单元
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499282
W. Weber, S. Prange, R. Thewes, E. Wohlrab
{"title":"A neuron MOS transistor-based multiplier cell","authors":"W. Weber, S. Prange, R. Thewes, E. Wohlrab","doi":"10.1109/IEDM.1995.499282","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499282","url":null,"abstract":"Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131747606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs 表面沟道应变si - p- mosfet中增强的空穴迁移率
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499251
K. Rim, J. Welser, J. Hoyt, J. Gibbons
{"title":"Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs","authors":"K. Rim, J. Welser, J. Hoyt, J. Gibbons","doi":"10.1109/IEDM.1995.499251","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499251","url":null,"abstract":"The strain dependence of the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers is reported for the first time. The hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Si/sub 1-x/Ge/sub x/ buffer layer increases. When compared to the device with x=0.1, the devices with x=0.22 and 0.29 exhibit hole mobility enhancement factors of 1.4 and 1.8, respectively. In spite of the high fixed charge in our gate oxides, the device with Ge content x=0.29 still exhibits a mobility 1.3 times that of bulk Si MOSFETs with state-of-the-art oxides. The first measurements of the transconductance enhancements in submicron strained-Si p-MOSFETs are also reported.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128373205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 106
A new physical model for the kink effect on InAlAs/InGaAs HEMTs InAlAs/InGaAs hemt扭结效应的新物理模型
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497214
Mark H Somervillet, Jes6s A Del Alamot, William Hoke
{"title":"A new physical model for the kink effect on InAlAs/InGaAs HEMTs","authors":"Mark H Somervillet, Jes6s A Del Alamot, William Hoke","doi":"10.1109/IEDM.1995.497214","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497214","url":null,"abstract":"New measurements providing direct evidence linking the kink effect and impact ionization in InAlAs/InGaAs HEMTs are reported. Current kink models are not consistent with our findings. We propose a new mechanism, barrier-induced hole pile-up at the source, to explain the kink. The new model is shown to be consistent with both room temperature and low temperature measurements. These results allow formulation of a simple equivalent circuit model of the kink.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116538428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Lateral backward diodes as strain sensors 作为应变传感器的横向后向二极管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499292
A. Friedrich, P. Besse, E. Fullin, R. Popovic
{"title":"Lateral backward diodes as strain sensors","authors":"A. Friedrich, P. Besse, E. Fullin, R. Popovic","doi":"10.1109/IEDM.1995.499292","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499292","url":null,"abstract":"We present a new type of lateral backward silicon diode intended to be used as a strain sensor. The devices are fabricated using a close-to-conventional silicon technology. The diodes have a prevailing tunnelling current around zero bias. They exhibit a high strain sensitivity and a low temperature coefficient of opposite sign to that of conventional piezoresistors.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122248526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SiGe base bipolar technology with 74 GHz f/sub max/ and 11 ps gate delay SiGe基双极技术，74ghz f/sub max/和11ps门延迟
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499324
T. Meister, H. Schafer, M. Franosch, W. Molzer, K. Aufinger, U. Scheler, C. Walz, H. Stolz, S. Boguth, J. Bock
{"title":"SiGe base bipolar technology with 74 GHz f/sub max/ and 11 ps gate delay","authors":"T. Meister, H. Schafer, M. Franosch, W. Molzer, K. Aufinger, U. Scheler, C. Walz, H. Stolz, S. Boguth, J. Bock","doi":"10.1109/IEDM.1995.499324","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499324","url":null,"abstract":"An epitaxial SiGe-base bipolar technology suited for very high performance mixed digital/analogue applications is presented. A key feature is the emitter/base process which is the obvious SiGe-base extension of the implanted base double-poly self-aligned emitter/base structure. The fabricated HBTs exhibit a maximum cut-off frequency f/sub T/ of 61 GHz, a maximum oscillation frequency f/sub max/ of 74 GHz and a record CML gate delay time of 11 ps.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116475883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
Simulation approach for achieving configuration independent poly-silicon gate etching 实现构型无关多晶硅栅极刻蚀的仿真方法
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497193
K. Harafuji, M. Ohkuni, H. Kubota, H. Nakagawa, A. Misaka
{"title":"Simulation approach for achieving configuration independent poly-silicon gate etching","authors":"K. Harafuji, M. Ohkuni, H. Kubota, H. Nakagawa, A. Misaka","doi":"10.1109/IEDM.1995.497193","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497193","url":null,"abstract":"Profile and dimension control mechanisms in poly-silicon gate etching are studied systematically by the use of a two-dimensional etching topography simulator. Reaction rates are calculated by taking into account interactions between incoming ion/radical fluxes and an ever-changing macroscopic adsorbed particle layer on the film surface. A qualitative guideline is presented for achieving both anisotropic etched-profile formation and the dimension difference minimization between the inner line pattern and the outermost line pattern in L&S.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134110541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High density plasma etch induced damage to thin gate oxide 高密度等离子蚀刻对薄栅极氧化物的损伤
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499204
S. Krishnan, S. Aur, G. Wilhite, R. Rajgopal
{"title":"High density plasma etch induced damage to thin gate oxide","authors":"S. Krishnan, S. Aur, G. Wilhite, R. Rajgopal","doi":"10.1109/IEDM.1995.499204","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499204","url":null,"abstract":"We report here severe charging caused by an inductively coupled plasma (ICP) etch, a high density plasma tool, on devices targeted for the 0.35 /spl mu/m technology mode. For the first time, direct evidence of a bi-directional charging mechanism is provided. Differential amplifiers connected to antennae exhibit offset voltage increase up to 300 mV. The lifetime of a nominal device in the presence of ICP charging is shown to reduce by a decade. Reported here for the first time is the immunity of SOI devices to such severe charging environments.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Interconnect scaling-the real limiter to high performance ULSI 互连扩展-高性能ULSI的真正限制因素
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499187
M. Bohr
{"title":"Interconnect scaling-the real limiter to high performance ULSI","authors":"M. Bohr","doi":"10.1109/IEDM.1995.499187","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499187","url":null,"abstract":"Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of /spl sim/2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129453395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 537
A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing 采用高温溅射和原位真空退火技术制备0.15 /spl μ m CMOS的新型盐化钴工艺
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499234
K. Inoue, K. Mikagi, H. Abiko, T. Kikkawa
{"title":"A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing","authors":"K. Inoue, K. Mikagi, H. Abiko, T. Kikkawa","doi":"10.1109/IEDM.1995.499234","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499234","url":null,"abstract":"A new cobalt (Co) salicide technology using high-temperature sputtering and in-situ vacuum annealing process has been developed. This technology is a simple process without additional ion implantation and metal deposition to promote silicidation and to suppress oxidation of Co film. No line width dependence of sheet resistances was achieved down to for 0.15 /spl mu/m gate electrode and 0.33 /spl mu/m for diffusion layer. Sheet resistance of 11 /spl Omega//sq. for both gate electrode and diffusion layer was obtained with 5 nm thick Co film (CoSi/sub 2/ 17.5 nm). By using this technology, 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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