实现构型无关多晶硅栅极刻蚀的仿真方法

K. Harafuji, M. Ohkuni, H. Kubota, H. Nakagawa, A. Misaka
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引用次数: 2

摘要

利用二维刻蚀形貌模拟器系统地研究了多晶硅栅极刻蚀中的轮廓和尺寸控制机理。反应速率的计算考虑了入射离子/自由基通量与薄膜表面不断变化的宏观吸附粒子层之间的相互作用。提出了实现各向异性蚀刻轮廓的形成以及在L&S中实现内线图案与最外线图案尺寸差最小化的定性准则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Simulation approach for achieving configuration independent poly-silicon gate etching
Profile and dimension control mechanisms in poly-silicon gate etching are studied systematically by the use of a two-dimensional etching topography simulator. Reaction rates are calculated by taking into account interactions between incoming ion/radical fluxes and an ever-changing macroscopic adsorbed particle layer on the film surface. A qualitative guideline is presented for achieving both anisotropic etched-profile formation and the dimension difference minimization between the inner line pattern and the outermost line pattern in L&S.
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