{"title":"A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing","authors":"K. Inoue, K. Mikagi, H. Abiko, T. Kikkawa","doi":"10.1109/IEDM.1995.499234","DOIUrl":null,"url":null,"abstract":"A new cobalt (Co) salicide technology using high-temperature sputtering and in-situ vacuum annealing process has been developed. This technology is a simple process without additional ion implantation and metal deposition to promote silicidation and to suppress oxidation of Co film. No line width dependence of sheet resistances was achieved down to for 0.15 /spl mu/m gate electrode and 0.33 /spl mu/m for diffusion layer. Sheet resistance of 11 /spl Omega//sq. for both gate electrode and diffusion layer was obtained with 5 nm thick Co film (CoSi/sub 2/ 17.5 nm). By using this technology, 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499234","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
A new cobalt (Co) salicide technology using high-temperature sputtering and in-situ vacuum annealing process has been developed. This technology is a simple process without additional ion implantation and metal deposition to promote silicidation and to suppress oxidation of Co film. No line width dependence of sheet resistances was achieved down to for 0.15 /spl mu/m gate electrode and 0.33 /spl mu/m for diffusion layer. Sheet resistance of 11 /spl Omega//sq. for both gate electrode and diffusion layer was obtained with 5 nm thick Co film (CoSi/sub 2/ 17.5 nm). By using this technology, 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.