{"title":"基于神经元MOS晶体管的乘法器单元","authors":"W. Weber, S. Prange, R. Thewes, E. Wohlrab","doi":"10.1109/IEDM.1995.499282","DOIUrl":null,"url":null,"abstract":"Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A neuron MOS transistor-based multiplier cell\",\"authors\":\"W. Weber, S. Prange, R. Thewes, E. Wohlrab\",\"doi\":\"10.1109/IEDM.1995.499282\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499282\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499282","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.
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