K. Ishimaru, M. Takahashi, M. Nishigohori, Y. Okayama, Y. Unno, F. Matsuoka, M. Kakumu
{"title":"双极安装CMOS技术，没有任何工艺步骤增加高速缓存SRAM","authors":"K. Ishimaru, M. Takahashi, M. Nishigohori, Y. Okayama, Y. Unno, F. Matsuoka, M. Kakumu","doi":"10.1109/IEDM.1995.499309","DOIUrl":null,"url":null,"abstract":"Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"205 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Bipolar installed CMOS technology without any process step increase for high speed cache SRAM\",\"authors\":\"K. Ishimaru, M. Takahashi, M. Nishigohori, Y. Okayama, Y. Unno, F. Matsuoka, M. Kakumu\",\"doi\":\"10.1109/IEDM.1995.499309\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"205 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499309\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499309","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bipolar installed CMOS technology without any process step increase for high speed cache SRAM
Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM.
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