O. Akcasu, J. Lu, A. Dalal, S. Mitra, L. Lev, N. Vassegihi, A. Pance, H. Hingarh, H. Basit
{"title":"“NET-AN”是一个全三维寄生互连分布式RLC提取器,适用于大型全芯片应用","authors":"O. Akcasu, J. Lu, A. Dalal, S. Mitra, L. Lev, N. Vassegihi, A. Pance, H. Hingarh, H. Basit","doi":"10.1109/IEDM.1995.499246","DOIUrl":null,"url":null,"abstract":"A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"\\\"NET-AN\\\" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications\",\"authors\":\"O. Akcasu, J. Lu, A. Dalal, S. Mitra, L. Lev, N. Vassegihi, A. Pance, H. Hingarh, H. Basit\",\"doi\":\"10.1109/IEDM.1995.499246\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499246\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
"NET-AN" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications
A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts.