Bipolar installed CMOS technology without any process step increase for high speed cache SRAM

Abstract

Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM.