2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers最新文献_第2页

High-performance MoS2 field-effect transistors enabled by chloride doping: Record low contact resistance (0.5 kΩ·µm) and record high drain current (460 µA/µm) 氯化物掺杂实现高性能MoS2场效应晶体管:创纪录的低接触电阻(0.5 kΩ·µm)和创纪录的高漏极电流(460µA/µm)

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894432

Lingming Yang, K. Majumdar, Yuchen Du, Han Liu, Heng Wu, M. Hatzistergos, P. Hung, R. Tieckelmann, W. Tsai, C. Hobbs, P. Ye

{"title":"High-performance MoS2 field-effect transistors enabled by chloride doping: Record low contact resistance (0.5 kΩ·µm) and record high drain current (460 µA/µm)","authors":"Lingming Yang, K. Majumdar, Yuchen Du, Han Liu, Heng Wu, M. Hatzistergos, P. Hung, R. Tieckelmann, W. Tsai, C. Hobbs, P. Ye","doi":"10.1109/VLSIT.2014.6894432","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894432","url":null,"abstract":"In this paper, we report a novel chemical doping technique to reduce the contact resistance (Rc) of transition metal dichalcogenides (TMDs) - eliminating two major roadblocks (namely, doping and high Rc) towards demonstration of high-performance TMDs field-effect transistors (FETs). By using 1,2 dichloroethane (DCE) as the doping reagent, we demonstrate an active n-type doping density > 2×1019 cm-3 in a few-layer MoS2 film. This enabled us to reduce the Rc value to a record low number of 0.5 kΩ·μm, which is ~10×lower than the control sample without doping. The corresponding specific contact resistivity (ρc) is found to decrease by two orders of magnitude. With such low Rc, we demonstrate 100 nm channel length (Lch) MoS2 FET with a drain current (Ids) of 460 μA/μm at Vds = 1.6 V, which is twice the best value reported so far on MoS2 FETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134255862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Strained Si1−xGex-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10nm node and beyond 应变Si1−xGex-on-insulator PMOS finfet具有优异的亚阈值泄漏，极高的短通道性能和10nm及以上节点的源注入速度

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894344

P. Hashemi, K. Balakrishnan, A. Majumdar, A. Khakifirooz, Wanki Kim, A. Baraskar, L. Yang, Kevin K. H. Chan, S. Engelmann, J. Ott, D. Antoniadis, E. Leobandung, Dae-gyu Park

{"title":"Strained Si1−xGex-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10nm node and beyond","authors":"P. Hashemi, K. Balakrishnan, A. Majumdar, A. Khakifirooz, Wanki Kim, A. Baraskar, L. Yang, Kevin K. H. Chan, S. Engelmann, J. Ott, D. Antoniadis, E. Leobandung, Dae-gyu Park","doi":"10.1109/VLSIT.2014.6894344","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894344","url":null,"abstract":"We demonstrate high performance (HP) s-SiGe pMOS finFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. We also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and LG~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe finFETs are strong candidates for future HP and low-power applications.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134495761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Direct measurement of the dynamic variability of 0.120µm2 SRAM cells in 28nm FD-SOI technology 采用28nm FD-SOI技术直接测量0.120µm2 SRAM细胞的动态变异性

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894415

J. El Husseini, X. Garros, A. Subirats, A. Makosiej, O. Weber, O. Thomas, V. Huard, X. Federspiel, G. Reimbold

引用次数: 2

A fast and low-voltage Cu complementary-atom-switch 1Mb array with high-temperature retention 一种具有高温保持的快速低压铜互补原子开关1Mb阵列

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894437

N. Banno, M. Tada, T. Sakamoto, M. Miyamura, K. Okamoto, N. Iguchi, T. Nohisa, H. Hada

引用次数: 11

A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory 一种新型电容耦合浮栅天线保护设计及其在3D NAND闪存中防止过程中充电效应的应用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894400

H. Lue, T. Yeh, Kuo-Ping Chang, T. Hsu, Y. Shih, Chih-Yuan Lu

引用次数: 3

Electrical and reliability characteristics of a scaled (∼30nm) tunnel barrier selector (W/Ta2O5/TaOx/TiO2/TiN) with excellent performance (JMAX > 107A/cm2) 具有优异性能(JMAX > 107A/cm2)的尺寸(~ 30nm)隧道势垒选择器(W/Ta2O5/TaOx/TiO2/TiN)的电气特性和可靠性

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894431

J. Woo, Jeonghwan Song, Kibong Moon, Ji Hyun Lee, E. Cha, A. Prakash, Daeseok Lee, Sangheon Lee, Jaesung Park, Y. Koo, Chan Gyung Park, H. Hwang

引用次数: 17

Demonstration of Ge pMOSFETs with 6 Å EOT using TaN/ZrO2/Zr-cap/n-Ge(100) gate stack fabricated by novel vacuum annealing and in-situ metal capping method 采用新型真空退火和原位金属封盖法制备TaN/ZrO2/Zr-cap/n-Ge(100)栅极堆制备6 Å EOT Ge pmosfet

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894377

Yunsang Shin, W. Chung, Yujin Seo, Choong-Ho Lee, D. Sohn, B. Cho

引用次数: 11

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond 模拟，射频和ESD器件的挑战和解决方案，为14nm FinFET技术和超越

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894378

Jagar Singh, C. Jerome, A. Wei, R. Miller, B. Arnaud, Cheng Lili, H. Zang, Punchihewa Kasun, Prabhu Manjunatha, Senapati Biswanath, Anil Kumar, S. Pandey, N. M. Iyer, Anurag Mittal, R. Carter, Lun Zhao, E. Manfred, S. Samavedam

引用次数: 12

Lowest variability SOI FinFETs having multiple Vt by back-biasing 通过反向偏置具有多个Vt的最低可变性SOI finfet

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894393

T. Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara

引用次数: 16

NbO2-based low power and cost effective 1S1R switching for high density cross point ReRAM Application 基于nbo2的低功耗和低成本的1S1R开关用于高密度交叉点ReRAM应用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894405

W. Kim, Hyun Min Lee, B. Kim, Kyooho Jung, T. Seong, S. Kim, H. C. Jung, H. Kim, Jong-Hee Yoo, H. Lee, S. Kim, Suock Chung, Kee-jeung Lee, Jung Hoon Lee, H. Kim, S. Lee, Jianhua Yang, Yoocharn Jeon, R. S. Williams

引用次数: 37