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Impact of contact and local interconnect scaling on logic performance 接触和局部互连尺度对逻辑性能的影响
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894406
S. Datta, R. Pandey, A. Agrawal, S. Gupta, R. Arghavani
{"title":"Impact of contact and local interconnect scaling on logic performance","authors":"S. Datta, R. Pandey, A. Agrawal, S. Gupta, R. Arghavani","doi":"10.1109/VLSIT.2014.6894406","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894406","url":null,"abstract":"We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114412677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Spatial mapping of non-uniform time-to-breakdown and physical evidence of defect clustering 非均匀故障时间的空间映射和缺陷聚类的物理证据
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894386
E. Wu, Baozhen Li, J. Stathis, B. Linder, T. Shaw
{"title":"Spatial mapping of non-uniform time-to-breakdown and physical evidence of defect clustering","authors":"E. Wu, Baozhen Li, J. Stathis, B. Linder, T. Shaw","doi":"10.1109/VLSIT.2014.6894386","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894386","url":null,"abstract":"For the first time, we report a spatial mapping methodology to directly obtain spatial BD distributions from TDDB data at wafer-scales. The results reveal BD defects are strongly clustered towards later stress times and explain the root-cause of non-Poisson area-scaling in agreement with recently developed time-dependent clustering model [3,4]. This methodology provides important detailed information for process diagnosis and improvement as well as realistic reliability assessment in future technologies as variability issues continue to rise.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application 使用所有类型的III-V型多栅极finfet进行7nm以下技术节点逻辑应用的静电和性能基准测试
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894420
R. Baek, D. Kim, T. Kim, C. Shin, W. Park, T. Michalak, C. Borst, S. C. Song, G. Yeap, R. Hill, C. Hobbs, W. Maszara, P. Kirsch
{"title":"Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application","authors":"R. Baek, D. Kim, T. Kim, C. Shin, W. Park, T. Michalak, C. Borst, S. C. Song, G. Yeap, R. Hill, C. Hobbs, W. Maszara, P. Kirsch","doi":"10.1109/VLSIT.2014.6894420","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894420","url":null,"abstract":"In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and interface trap(Dit) effects on electrostatic of III-V multi-gate(MG) nMOSFET which is critical to device scaling, we proposed a device design strategy for sub 7nm technology node.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123041808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high-density logic CMOS process compatible non-volatile memory for sub-28nm technologies 一种高密度逻辑CMOS工艺兼容的非易失性存储器，用于sub-28nm技术
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894353
R. Shen, Meng-Yi Wu, Hsin-Ming Chen, C. Lu
{"title":"A high-density logic CMOS process compatible non-volatile memory for sub-28nm technologies","authors":"R. Shen, Meng-Yi Wu, Hsin-Ming Chen, C. Lu","doi":"10.1109/VLSIT.2014.6894353","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894353","url":null,"abstract":"Various product applications bring up with increasing demands of logic NVM IP in advanced technology nodes. Encryption, security, functionality, and identification setting become indispensable in communication and high-end consumer electronics. A non-volatile memory cell, using anti-fuse programming mechanism to achieve high density and excellent data storage lifetime, is proposed. The unique cell design and operation scheme realize low programming-inhibit leakage current, fast program speed, and robust data retention. The memory macro is successfully demonstrated for one-time and multi-time programming applications with its full compatibility to sub-28nm and FinFET processes.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Band-to-band tunneling current enhancement utilizing isoelectronic trap and its application to TFETs 利用等电子阱的带对带隧道电流增强及其在tfet中的应用
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894370
T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, M. Masahara, T. Yasuda, H. Ota
{"title":"Band-to-band tunneling current enhancement utilizing isoelectronic trap and its application to TFETs","authors":"T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, M. Masahara, T. Yasuda, H. Ota","doi":"10.1109/VLSIT.2014.6894370","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894370","url":null,"abstract":"For the first time, we propose a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. We have demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128045075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A novel curved CMOS image sensor integrated with imaging system 一种集成成像系统的新型曲面CMOS图像传感器
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894341
Ezaki Takayuki, Itonaga Kazuichiro, Arimura Toshiyuki, M. Keiji, Kondo Goro, Terahata Kazuhide, Shinsaku Makimoto, Baba Masakazu, Honda Yasunori, Bori Seigo, Kai Toru, Kasahara Keijyu, Nagano Mitsuhiro, Kimura Masayuki, Kimura Yoshinori
{"title":"A novel curved CMOS image sensor integrated with imaging system","authors":"Ezaki Takayuki, Itonaga Kazuichiro, Arimura Toshiyuki, M. Keiji, Kondo Goro, Terahata Kazuhide, Shinsaku Makimoto, Baba Masakazu, Honda Yasunori, Bori Seigo, Kai Toru, Kasahara Keijyu, Nagano Mitsuhiro, Kimura Masayuki, Kimura Yoshinori","doi":"10.1109/VLSIT.2014.6894341","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894341","url":null,"abstract":"We realized an ultimately advanced imaging system that comprises a hemi-spherically curved, back-illuminated CMOS image sensor (BIS) and integrated lens which doubles the sensitivity at the edge of the image circle and increases the sensitivity at the center of the image circle by a factor of 1.4 with one-fifth lower dark current (Jd) than that of a planar BIS. Because the lens field curvature aberration (Afc) was overcome in principle by the curved sensor itself, the curved BIS enables higher system sensitivity through design of a brighter lens with a smaller F number (Fn) than is possible with a planar BIS. At the same time, we controlled the tensile stress of the BIS chip to produce a curved shape that widens the energy band-gap (Eg) to obtain a lower Jd.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128126771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
3D CMOS-MEMS stacking with TSV-less and face-to-face direct metal bonding 三维CMOS-MEMS叠层与TSV-less面对面直接金属键合
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894410
S. L. Chua, A. Razzaq, K. H. Wee, K. Li, H. Yu, C. Tan
{"title":"3D CMOS-MEMS stacking with TSV-less and face-to-face direct metal bonding","authors":"S. L. Chua, A. Razzaq, K. H. Wee, K. Li, H. Yu, C. Tan","doi":"10.1109/VLSIT.2014.6894410","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894410","url":null,"abstract":"CMOS readout circuit is stacked on MEMS accelerometer using face-to-face (F2F) direct metal bonding. F2F bonding provides smaller form factor, latency, and power consumption. The CMOS chip acts as an active cap that encapsulates and provides interconnect routing to the MEMS chip. Metal bonding (Al-Au) was achieved at 300°C/10min/50N. The bond quality meets the requirements during shear and helium leak tests. The stacked CMOS/MEMS chip is verified to be functional and sustains shock test of 500g.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A double-density dual-mode phase change memory using a novel background storage scheme 一种采用新型后台存储方案的双密度双模相变存储器
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894382
J. Y. Wu, M. Lee, W. Khwa, H. C. Lu, H. Li, Y. Chen, M. BrightSky, T. S. Chen, T. Wang, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam
{"title":"A double-density dual-mode phase change memory using a novel background storage scheme","authors":"J. Y. Wu, M. Lee, W. Khwa, H. C. Lu, H. Li, Y. Chen, M. BrightSky, T. S. Chen, T. Wang, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam","doi":"10.1109/VLSIT.2014.6894382","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894382","url":null,"abstract":"Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129331098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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