K. Majumdar, R. Clark, T. Ngai, K. Tapily, S. Consiglio, E. Bersch, K. Matthews, E. Stinzianni, Y. Trickett, G. Nakamura, C. Wajda, G. Leusink, H. Chong, V. Kaushik, J. Woicik, C. Hobbs, P. Kirsch
{"title":"Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure","authors":"K. Majumdar, R. Clark, T. Ngai, K. Tapily, S. Consiglio, E. Bersch, K. Matthews, E. Stinzianni, Y. Trickett, G. Nakamura, C. Wajda, G. Leusink, H. Chong, V. Kaushik, J. Woicik, C. Hobbs, P. Kirsch","doi":"10.1109/VLSIT.2014.6894423","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894423","url":null,"abstract":"We demonstrate a 300mm wafer scale conformal contact process to achieve uniform ultra-low specific contact resistivity (ρ<sub>c</sub>) for metal/high-k/n<sup>+</sup>Si (MIS) contacts. To achieve conformal contacts, we use a sidewall TLM (STLM) test structure that helps to minimize current crowding effect and variability. A systematic study is provided by varying doping density (N<sub>D</sub>), high-k material (LaO<sub>x</sub>, ZrO<sub>x</sub> and TiO<sub>x</sub>) and high-k thickness (t<sub>d</sub>) to optimize ρ<sub>c</sub>. The obtained ρ<sub>c</sub> and its uniformity are found to be comparable with standard nickel silicide technology, with a possibility of further improvement by use of lower work-function metal.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lisoni, A. Arreghini, G. Congedo, M. Toledano-Luque, I. Toqué-Trésonne, K. Huet, E. Capogreco, L. Liu, C. Tan, R. Degraeve, G. Van den bosch, J. van Houdt
{"title":"Laser thermal anneal of polysilicon channel to boost 3D memory performance","authors":"J. Lisoni, A. Arreghini, G. Congedo, M. Toledano-Luque, I. Toqué-Trésonne, K. Huet, E. Capogreco, L. Liu, C. Tan, R. Degraeve, G. Van den bosch, J. van Houdt","doi":"10.1109/VLSIT.2014.6894346","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894346","url":null,"abstract":"We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127316537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Hofmann, K. Knobloch, Christian Peters, R. Allinger
{"title":"Comprehensive statistical investigation of STT-MRAM thermal stability","authors":"K. Hofmann, K. Knobloch, Christian Peters, R. Allinger","doi":"10.1109/VLSIT.2014.6894367","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894367","url":null,"abstract":"The thermal stability Δ is a key parameter of the MRAM technology. It determines the current induced switching behavior as well as the reliability performance of e.g. data retention and read-disturb. Therefore a highly accurate assessment of Δ is mandatory for a successful MRAM technology development. In this paper we present a verification methodology based on the statistical data of a 8Mb test vehicle revealing a wide Δ distribution of ~17%.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127496538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. H. Lee, C. Lu, T. Nishimura, K. Nagashio, A. Toriumi
{"title":"Thermally robust CMOS-aware Ge MOSFETs with high mobility at high-carrier densities on a single orientation Ge substrate","authors":"C. H. Lee, C. Lu, T. Nishimura, K. Nagashio, A. Toriumi","doi":"10.1109/VLSIT.2014.6894394","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894394","url":null,"abstract":"This paper presents the superior electron and hole mobility on a single orientation Ge substrate for compact and cost-effective CMOS applications. The different scattering mechanisms of electron and hole mobility are discussed for understanding carrier transport physics. On the basis of this understanding, the highest electron mobility of 437 cm2/Vs and hole mobility of 213 cm2/Vs at Ns=1e13 cm-2 in sub-nm EOT Ge(111) FETs are demonstrated.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"38 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Physics based PBTI model for accelerated estimation of 10 year lifetime","authors":"S. Zafar, A. Kerber, R. Muralidhar","doi":"10.1109/VLSIT.2014.6894388","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894388","url":null,"abstract":"Threshold voltages (Vt) in high κ nFETs are observed to shift under prolonged positive gate bias stressing. This bias induced Vt shift (ΔVt) is referred as PBTI and is an important reliability issue. In this paper, we extend a previously proposed PBTI model to include de-trapping kinetics. The proposed model is verified by comparing calculated results with PBTI data measured over a wide range of stress conditions. Using the proposed model, an accelerated method for estimating 10 year lifetime is presented. This method does not require a-priori knowledge of parameters and uses a combination of voltage ramp and constant voltage measurements to estimate model parameters with the total measurement time <; 1 hour. Using these extracted parameters and the model equations, 10 year lifetimes are estimated at different stress voltages.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Villalon, C. Le Royer, P. Nguyen, S. Barraud, F. Glowacki, A. Revelant, L. Selmi, S. Cristoloveanu, L. Tosti, C. Vizioz, J. Hartmann, N. Bernier, B. Previtali, C. Tabone, F. Allain, S. Martinie, O. Rozeau, M. Vinet
{"title":"First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm","authors":"A. Villalon, C. Le Royer, P. Nguyen, S. Barraud, F. Glowacki, A. Revelant, L. Selmi, S. Cristoloveanu, L. Tosti, C. Vizioz, J. Hartmann, N. Bernier, B. Previtali, C. Tabone, F. Allain, S. Martinie, O. Rozeau, M. Vinet","doi":"10.1109/VLSIT.2014.6894369","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894369","url":null,"abstract":"We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si<sub>1-x</sub>Ge<sub>x</sub> (x=0, 0.2, 0.25) nanowires, Si<sub>0.7</sub>Ge<sub>0.3</sub> Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W<sup>-3</sup> dependence of ON current (I<sub>ON</sub>) per wire. The fabricated devices exhibit higher I<sub>ON</sub> than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mitard, L. Witters, R. Loo, S. H. Lee, J. W. Sun, J. Franco, L. Ragnarsson, A. Brand, X. Lu, N. Yoshida, G. Eneman, D. Brunco, M. Vorderwestner, P. Storck, A. Milenin, A. Hikavyy, N. Waldron, P. Favia, D. Vanhaeren, A. Vanderheyden, R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. Lee, N. Horiguchi, N. Collaert, A. Thean
{"title":"15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process","authors":"J. Mitard, L. Witters, R. Loo, S. H. Lee, J. W. Sun, J. Franco, L. Ragnarsson, A. Brand, X. Lu, N. Yoshida, G. Eneman, D. Brunco, M. Vorderwestner, P. Storck, A. Milenin, A. Hikavyy, N. Waldron, P. Favia, D. Vanhaeren, A. Vanderheyden, R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. Lee, N. Horiguchi, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2014.6894391","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894391","url":null,"abstract":"An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET<sub>INV</sub>-normalized G<sub>M,SAT,INT</sub> of 6.7 nm.mS/μm, the Si<sub>0.3</sub>Ge<sub>0.7</sub> / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130353775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. H. Kim, Y. Ikku, M. Yokoyama, R. Nakane, J. Li, Y. Kao, M. Takenaka, S. Takagi
{"title":"High performance InGaAs-on-insulator MOSFETs on Si by novel direct wafer bonding technology applicable to large wafer size Si","authors":"S. H. Kim, Y. Ikku, M. Yokoyama, R. Nakane, J. Li, Y. Kao, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2014.6894352","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894352","url":null,"abstract":"In this paper, we present first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by direct wafer bonding (DWB) process using InGaAs channels grown on 4-inch Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement of 3 × against Si MOSFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Goux, A. Fantini, A. Redolfi, C. Y. Chen, F. Shi, R. Degraeve, Y. Chen, Thomas Witters, Guido Groeseneken, Malgorzata Jurczak
{"title":"Role of the Ta scavenger electrode in the excellent switching control and reliability of a scalable low-current operated TiNTa2O5Ta RRAM device","authors":"L. Goux, A. Fantini, A. Redolfi, C. Y. Chen, F. Shi, R. Degraeve, Y. Chen, Thomas Witters, Guido Groeseneken, Malgorzata Jurczak","doi":"10.1109/VLSIT.2014.6894401","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894401","url":null,"abstract":"We engineer a scalable and CMOS-friendly RRAM stack using down to 3nm ALD-based Ta<sub>2</sub>O<sub>5</sub>. The 20nm-sized TiNTa<sub>2</sub>O<sub>5</sub>Ta device operated at 50μA exhibits ultra-fast write (~5ns) at moderate voltage (<;2V) with >10<sup>9</sup> write endurance. We also demonstrate excellent disturb and retention characteristics, which we relate to the appropriate tuning of the oxygen chemical-potential profile along the filament by means of the Ta scavenger material and thickness.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128035806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Nallapati, J. Zhu, J. Wang, J. Sheu, K. Cheng, C. Gan, D. Yang, M. Cai, J. Cheng, L. Ge, Y. Chen, R. Bucki, B. Bowers, F. Vang, X. Chen, O. Kwon, S. Yoon, C. C. Wu, P. Chidambaram, M. Cao, J. Fischer, E. Terzioglu, Y. Mii, G. Yeap
{"title":"Cost and power/performance optimized 20nm SoC technology for advanced mobile devices","authors":"G. Nallapati, J. Zhu, J. Wang, J. Sheu, K. Cheng, C. Gan, D. Yang, M. Cai, J. Cheng, L. Ge, Y. Chen, R. Bucki, B. Bowers, F. Vang, X. Chen, O. Kwon, S. Yoon, C. C. Wu, P. Chidambaram, M. Cao, J. Fischer, E. Terzioglu, Y. Mii, G. Yeap","doi":"10.1109/VLSIT.2014.6894414","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894414","url":null,"abstract":"A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130177412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}