Laser thermal anneal of polysilicon channel to boost 3D memory performance

Abstract

We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.