First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

A. Villalon, C. Le Royer, P. Nguyen, S. Barraud, F. Glowacki, A. Revelant, L. Selmi, S. Cristoloveanu, L. Tosti, C. Vizioz, J. Hartmann, N. Bernier, B. Previtali, C. Tabone, F. Allain, S. Martinie, O. Rozeau, M. Vinet
{"title":"First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm","authors":"A. Villalon, C. Le Royer, P. Nguyen, S. Barraud, F. Glowacki, A. Revelant, L. Selmi, S. Cristoloveanu, L. Tosti, C. Vizioz, J. Hartmann, N. Bernier, B. Previtali, C. Tabone, F. Allain, S. Martinie, O. Rozeau, M. Vinet","doi":"10.1109/VLSIT.2014.6894369","DOIUrl":null,"url":null,"abstract":"We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si<sub>1-x</sub>Ge<sub>x</sub> (x=0, 0.2, 0.25) nanowires, Si<sub>0.7</sub>Ge<sub>0.3</sub> Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W<sup>-3</sup> dependence of ON current (I<sub>ON</sub>) per wire. The fabricated devices exhibit higher I<sub>ON</sub> than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"47","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894369","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 47

Abstract

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W-3 dependence of ON current (ION) per wire. The fabricated devices exhibit higher ION than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.
离子超过700µA/µm的应变SiGe纳米线tfet的首次演示
我们首次采用cmos兼容的工艺流程获得了高性能纳米线(NW)隧道场效应管(TFET),该工艺流程具有压缩应变Si1-xGex (x= 0,0.2, 0.25)纳米线,Si0.7Ge0.3源极和漏极以及高k /金属栅极。纳米线结构极大地改善了静电性能,而低带隙通道(SiGe)提供了更大的带对带隧道(tbbt)电流,以解决低导通电流的挑战。我们分析了这些改进对tfet的影响,并将它们与MOSFET进行了比较。研究了纳米线宽度对TFET器件的影响,显示了单线on电流(ION)的W-3依赖性。所制备的器件具有比以往报道的更高的离子,离子值高达760μA/μm,平均亚阈值斜率(SS)小于80mV/dec。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
CiteScore
3.40
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信