J. Mitard, L. Witters, R. Loo, S. H. Lee, J. W. Sun, J. Franco, L. Ragnarsson, A. Brand, X. Lu, N. Yoshida, G. Eneman, D. Brunco, M. Vorderwestner, P. Storck, A. Milenin, A. Hikavyy, N. Waldron, P. Favia, D. Vanhaeren, A. Vanderheyden, R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. Lee, N. Horiguchi, N. Collaert, A. Thean
{"title":"15nm-WFIN高性能低缺陷应变锗pfinfet低温STI-last工艺","authors":"J. Mitard, L. Witters, R. Loo, S. H. Lee, J. W. Sun, J. Franco, L. Ragnarsson, A. Brand, X. Lu, N. Yoshida, G. Eneman, D. Brunco, M. Vorderwestner, P. Storck, A. Milenin, A. Hikavyy, N. Waldron, P. Favia, D. Vanhaeren, A. Vanderheyden, R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. Lee, N. Horiguchi, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2014.6894391","DOIUrl":null,"url":null,"abstract":"An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET<sub>INV</sub>-normalized G<sub>M,SAT,INT</sub> of 6.7 nm.mS/μm, the Si<sub>0.3</sub>Ge<sub>0.7</sub> / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process\",\"authors\":\"J. Mitard, L. Witters, R. Loo, S. H. Lee, J. W. Sun, J. Franco, L. Ragnarsson, A. Brand, X. Lu, N. Yoshida, G. Eneman, D. Brunco, M. Vorderwestner, P. Storck, A. Milenin, A. Hikavyy, N. Waldron, P. Favia, D. Vanhaeren, A. Vanderheyden, R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. Lee, N. Horiguchi, N. Collaert, A. Thean\",\"doi\":\"10.1109/VLSIT.2014.6894391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET<sub>INV</sub>-normalized G<sub>M,SAT,INT</sub> of 6.7 nm.mS/μm, the Si<sub>0.3</sub>Ge<sub>0.7</sub> / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.
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