2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers最新文献_第9页

TSV technology and challenges for 3D stacked DRAM 3D堆叠DRAM的TSV技术与挑战

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894397

Chang Yeol Lee, Sungchul Kim, Hongshin Jun, Kyung Whan Kim, S. Hong

引用次数: 6

Embedded STT-MRAM for energy-efficient and cost-effective mobile systems 嵌入式STT-MRAM用于节能和经济高效的移动系统

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894354

Seung H. Kang

引用次数: 50

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins 基于Si鳍外延包覆的高迁移率Si0.55Ge0.45 p沟道finfet的性能和可靠性

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894360

H. Mertens, R. Ritzenthaler, A. Hikavyy, J. Franco, J. Lee, D. Brunco, G. Eneman, L. Witters, J. Mitard, S. Kubicek, K. Devriendt, D. Tsvetanova, A. Milenin, C. Vrancken, J. Geypen, H. Bender, G. Groeseneken, W. Vandervorst, K. Barla, N. Collaert, N. Horiguchi, A. Thean

引用次数: 12

Ge CMOS: Breakthroughs of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D Ge CMOS:非场效应管(Imax=714 mA/mm, gmax=590 mS/mm)在嵌入式通道和S/D上的突破

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894374

Heng Wu, M. Si, Lin Dong, Jingyun Zhang, P. Ye

引用次数: 20

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays 迈向高速、容写干扰的3D垂直RRAM阵列

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894434

Hong-Yu Chen, B. Gao, Haitong Li, Rui Liu, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Zizhen Jiang, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang, Shimeng Yu, Y. Nishi, H. Wong

引用次数: 13

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering 利用源结工程深入研究隧道场效应管的低频噪声特性

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894371

Qianqian Huang, Ru Huang, Cheng Chen, Chunlei Wu, Jiaxin Wang, Chao Wang, Yangyuan Wang

{"title":"Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering","authors":"Qianqian Huang, Ru Huang, Cheng Chen, Chunlei Wu, Jiaxin Wang, Chao Wang, Yangyuan Wang","doi":"10.1109/VLSIT.2014.6894371","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894371","url":null,"abstract":"The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f2 LFN dependence can be observed in large TFETs with large device to device variability, as well as high noise. It is found that the “active” traps responsible for the noise mechanism are located in the area where electron-hole pairs generated by non-local BTBT, and the trap located at the maximum junction electric field tends to have relatively weak impacts on the TFET noise. With new abrupt tunnel junction design, it is observed that the device variability can be effectively alleviated with much lower noise level. In addition, a single-trap-induced RTS noise in TFETs with different source junction design is also experimentally investigated. New features, including strong VD dependence of RTS parameters and significantly high amplitude (~28%), indicate the desirable requirement for the source junction optimization in TFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"53 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132973484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture 先进的1.1um像素CMOS图像传感器，3D堆叠架构

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894429

J. C. Liu, D. Yaung, J. Sze, C. Wang, Gene Hung, C. Wang, T. Hsu, R. Lin, T. Wang, W. D. Wang, H. Cheng, J. Lin, S. Tsai, S. Tsai, C. Chuang, W. Hsu, S. Y. Chen, K. C. Huang, W. H. Wu, S. Takahashi, Y. Tu, C. Tsai, R. Lee, W. P. Mo, F. J. Shiu, Y. Chao, S. Wuu

{"title":"Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture","authors":"J. C. Liu, D. Yaung, J. Sze, C. Wang, Gene Hung, C. Wang, T. Hsu, R. Lin, T. Wang, W. D. Wang, H. Cheng, J. Lin, S. Tsai, S. Tsai, C. Chuang, W. Hsu, S. Y. Chen, K. C. Huang, W. H. Wu, S. Takahashi, Y. Tu, C. Tsai, R. Lee, W. P. Mo, F. J. Shiu, Y. Chao, S. Wuu","doi":"10.1109/VLSIT.2014.6894429","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894429","url":null,"abstract":"This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor performance can be significantly minimized. In addition, for the first time, the degradation of stacked pixel performance during the folded circuit operation under sensor array is found and improved. The final stacked sensor exhibits the comparable pixel performances to conventional BSI. Furthermore, stacked architecture provides the opportunity to enhance sensor performance by the separate process tuning for sensor wafers (without any effect on ASIC wafers), leading to a further improvement of dark performance.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond 采用导电金属栅极堆栈调谐，可用于10nm及以上节点，具有Multi-VT选项的高可扩展体FinFET器件

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894359

L. Ragnarsson, S. Chew, H. Dekkers, M. T. Luque, B. Parvais, A. De Keersgieter, K. Devriendt, A. Van Ammel, T. Schram, N. Yoshida, A. Phatak, K. Han, B. Colombeau, A. Brand, N. Horiguchi, A. Thean

引用次数: 26

Systematic study of RTN in nanowire transistor and enhanced RTN by hot carrier injection and negative bias temperature instability 系统研究了纳米线晶体管中的RTN，并通过热载流子注入和负偏置温度不稳定性增强了RTN

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894417

K. Ota, M. Saitoh, C. Tanaka, D. Matsushita, T. Numata

引用次数: 11

Further understandings on random telegraph signal noise through comprehensive studies on large time constant variation and its strong correlations to thermal activation energies 通过对大时间常数变化及其与热活化能的强相关性的综合研究，进一步认识随机电报信号噪声

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894418

Jiezhi Chen, Y. Higashi, Koichi Kato, Y. Mitani

引用次数: 8