{"title":"Ge CMOS:非场效应管(Imax=714 mA/mm, gmax=590 mS/mm)在嵌入式通道和S/D上的突破","authors":"Heng Wu, M. Si, Lin Dong, Jingyun Zhang, P. Ye","doi":"10.1109/VLSIT.2014.6894374","DOIUrl":null,"url":null,"abstract":"We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (I<sub>max</sub>) of 714 mA/mm and trans-conductance (g<sub>max</sub>) of 590 mS/mm, high I<sub>on</sub>/I<sub>off</sub> ratio of 1×10<sup>5</sup> are archived at channel length (L<sub>ch</sub>) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted in sub-100 nm region down to 25 nm for the first time. Considering the Fermi level (E<sub>F</sub>) pining near the valence band edge (EV) of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the JL accumulation-mode (JAM) Ge nFET is proposed.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Ge CMOS: Breakthroughs of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D\",\"authors\":\"Heng Wu, M. Si, Lin Dong, Jingyun Zhang, P. Ye\",\"doi\":\"10.1109/VLSIT.2014.6894374\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (I<sub>max</sub>) of 714 mA/mm and trans-conductance (g<sub>max</sub>) of 590 mS/mm, high I<sub>on</sub>/I<sub>off</sub> ratio of 1×10<sup>5</sup> are archived at channel length (L<sub>ch</sub>) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted in sub-100 nm region down to 25 nm for the first time. Considering the Fermi level (E<sub>F</sub>) pining near the valence band edge (EV) of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the JL accumulation-mode (JAM) Ge nFET is proposed.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894374\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894374","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
摘要
本文报道了一种基于嵌入式通道和源/漏(S/D)的Ge CMOS技术的新实现方法。无结(JL) nfet和pfet都集成在一个通用的GeOI衬底上。凹进式S/D工艺极大地改善了锗氮接触。在通道长度为60 nm时,nfet的最大漏极电流(Imax)为714 mA/mm,跨电导(gmax)为590 mS/mm,离子/ off比(1×105)高。首次在亚100nm至25nm的区域进行了Ge非场效应管的可扩展性研究。考虑到Ge价带边缘(EV)附近的费米能级(EF)衰减,提出了一种由反转模式(IM) Ge fet和JL积累模式(JAM) Ge fet组成的新型混合CMOS结构。
Ge CMOS: Breakthroughs of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D
We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted in sub-100 nm region down to 25 nm for the first time. Considering the Fermi level (EF) pining near the valence band edge (EV) of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the JL accumulation-mode (JAM) Ge nFET is proposed.