3D堆叠DRAM的TSV技术与挑战

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI:10.1109/VLSIT.2014.6894397

Chang Yeol Lee, Sungchul Kim, Hongshin Jun, Kyung Whan Kim, S. Hong

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引用次数: 6

摘要

介绍了在DRAM技术中成功地集成了Via-middle TSV工艺，并解决了主要工艺问题。讨论了TSV开/短的快速检测以及在选择修复方案时如何权衡。TSV体积缩小所需的工艺开发，以降低驱动TSV的动态功率。快速铜泄漏监测方法是保持良好质量和晶圆厂工艺控制的关键。

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TSV technology and challenges for 3D stacked DRAM

A successful integration of Via-middle TSV process in DRAM technology with major process issues is introduced. Fast TSV open/short detection and how to trade-off in choice repair scheme is discussed. Process development for TSV volume shrink required to reduce dynamic power for driving TSV. Fast Cu leak monitor method is essential to sustaining good quality and Fab process control.

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来源期刊

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

CiteScore

3.40

自引率

0.00%

发文量