N. Waldron, C. Merckling, W. Guo, P. Ong, L. Teugels, S. Ansar, D. Tsvetanova, F. Sebaai, D. V. van Dorp, A. Milenin, D. Lin, L. Nyns, J. Mitard, A. Pourghaderi, B. Douhard, O. Richard, H. Bender, G. Boccardi, M. Caymax, M. Heyns, W. Vandervorst, K. Barla, N. Collaert, A. Thean
{"title":"An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates","authors":"N. Waldron, C. Merckling, W. Guo, P. Ong, L. Teugels, S. Ansar, D. Tsvetanova, F. Sebaai, D. V. van Dorp, A. Milenin, D. Lin, L. Nyns, J. Mitard, A. Pourghaderi, B. Douhard, O. Richard, H. Bender, G. Boccardi, M. Caymax, M. Heyns, W. Vandervorst, K. Barla, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2014.6894349","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894349","url":null,"abstract":"InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122524363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ju Hyun Kim, W. C. Lim, U. Pi, J. Lee, W. Kim, J. H. Kim, K. Kim, Y. Park, S. H. Park, M. A. Kang, Y. Kim, W. Kim, S. Kim, J. Park, S. C. Lee, Y. J. Lee, J. Yoon, S. C. Oh, S. O. Park, S. Jeong, S. Nam, H. K. Kang, E. Jung
{"title":"Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell","authors":"Ju Hyun Kim, W. C. Lim, U. Pi, J. Lee, W. Kim, J. H. Kim, K. Kim, Y. Park, S. H. Park, M. A. Kang, Y. Kim, W. Kim, S. Kim, J. Park, S. C. Lee, Y. J. Lee, J. Yoon, S. C. Oh, S. O. Park, S. Jeong, S. Nam, H. K. Kang, E. Jung","doi":"10.1109/VLSIT.2014.6894366","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894366","url":null,"abstract":"Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Zaitsu, K. Tatsumura, M. Matsumoto, Masato Oda, S. Fujita, S. Yasuda
{"title":"Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme","authors":"K. Zaitsu, K. Tatsumura, M. Matsumoto, Masato Oda, S. Fujita, S. Yasuda","doi":"10.1109/VLSIT.2014.6894355","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894355","url":null,"abstract":"Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors (MTrs.) and low-voltage switching transistors (SwTrs.) are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the SwTrs. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating (PG) that offers low-power FPGA operation.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121450944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Clarke, Christopher George, C. Jezewski, A. M. Caro, D. Michalak, J. Torres
{"title":"Process technology scaling in an increasingly interconnect dominated world","authors":"J. Clarke, Christopher George, C. Jezewski, A. M. Caro, D. Michalak, J. Torres","doi":"10.1109/VLSIT.2014.6894407","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894407","url":null,"abstract":"The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116862041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Sunamura, N. Inoue, N. Furutake, S. Saito, M. Narihiro, M. Hane, Y. Hayashi
{"title":"Enhanced drivability of high-Vbd dual-oxide-based complementary BEOL-FETs for compact on-chip pre-driver applications","authors":"H. Sunamura, N. Inoue, N. Furutake, S. Saito, M. Narihiro, M. Hane, Y. Hayashi","doi":"10.1109/VLSIT.2014.6894426","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894426","url":null,"abstract":"Enhanced current drivability of BEOL-process-compatible dual-oxide complementary BEOL-FETs on LSI-interconnects (Fig. 1) with just two additional masks to the state-of-the-art BEOL process is demonstrated, aiming at high-Vbd pre-driver operation. We have developed processes so that IGZO-based NFETs have lower ARon as compared to currently available Si power devices (Fig. 6). We also developed new SnO processes, realizing a 30× Ion boost for PFETs. Dual oxide semiconductor channels are integrated to form BEOL-CMOS inverters with stable and sharp cut-off characteristics (Figs. 8 and 9) for lower power operation, leading to a successful operation of an integrated 6T-SRAM cell (Fig. 11). Pre-driver capability of NFET inverters is demonstrated with MCU-controlled operation of brushless DC (BLDC) motors (Fig. 12). This technology is a strong candidate to realize high-Vbd pre-drivers and low-power logic on BEOL, which gives standard LSIs a special add-on function for smart society applications.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, R. Xie, H. Shang, E. Alptekin, D. Bae, G. Bae, C. Boye, H. Cai, D. Chanemougame, R. Chao, K. Cheng, J. Cho, K. Choi, B. Hamieh, J. Hong, T. Hook, L. Jang, J. Jung, R. Jung, D. Lee, B. Lherron, R. Kambhampati, B. Kim, H. Kim, K. Kim, T. Kim, S. Ko, F. Lie, D. Liu, H. Mallela, E. Mclellan, S. Mehta, P. Montanini, M. Mottura, J. Nam, S. Nam, F. Nelson, I. Ok, C. Park, Y. Park, A. Paul, C. Prindle, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze, S. Seo, J. Shearer, R. Southwick, R. Sreenivasan, S. Stieg, J. Strane, X. Sun, M. Sung, C. Surisetty, G. Tsutsui, N. Tripathi, R. Vega, C. Waskiewicz, M. Weybright, C. Yeh, H. Bu, S. Burns, D. Canaperi, M. Celik, M. Colburn, H. Jagannathan, S. Kanakasabaphthy, W. Kleemeier, L. Liebmann, D. Mcherron, P. Oldiges, V. Paruchuri, T. Spooner, J. Stathis, R. Divakaruni, T. Gow, J. Iacoponi, J. Jenq, R. Sampson, M. Khare
{"title":"A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI","authors":"K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, R. Xie, H. Shang, E. Alptekin, D. Bae, G. Bae, C. Boye, H. Cai, D. Chanemougame, R. Chao, K. Cheng, J. Cho, K. Choi, B. Hamieh, J. Hong, T. Hook, L. Jang, J. Jung, R. Jung, D. Lee, B. Lherron, R. Kambhampati, B. Kim, H. Kim, K. Kim, T. Kim, S. Ko, F. Lie, D. Liu, H. Mallela, E. Mclellan, S. Mehta, P. Montanini, M. Mottura, J. Nam, S. Nam, F. Nelson, I. Ok, C. Park, Y. Park, A. Paul, C. Prindle, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze, S. Seo, J. Shearer, R. Southwick, R. Sreenivasan, S. Stieg, J. Strane, X. Sun, M. Sung, C. Surisetty, G. Tsutsui, N. Tripathi, R. Vega, C. Waskiewicz, M. Weybright, C. Yeh, H. Bu, S. Burns, D. Canaperi, M. Celik, M. Colburn, H. Jagannathan, S. Kanakasabaphthy, W. Kleemeier, L. Liebmann, D. Mcherron, P. Oldiges, V. Paruchuri, T. Spooner, J. Stathis, R. Divakaruni, T. Gow, J. Iacoponi, J. Jenq, R. Sampson, M. Khare","doi":"10.1109/VLSIT.2014.6894342","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894342","url":null,"abstract":"A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129285411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Meng, X. Xue, Y. L. Song, J. G. Yang, B. Chen, Y. Y. Lin, Q. Zou, R. Huang, J. Wu
{"title":"Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement","authors":"Y. Meng, X. Xue, Y. L. Song, J. G. Yang, B. Chen, Y. Y. Lin, Q. Zou, R. Huang, J. Wu","doi":"10.1109/VLSIT.2014.6894435","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894435","url":null,"abstract":"We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO<sub>x</sub>/WO<sub>x</sub> bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10<sup>7</sup> to 10<sup>9</sup>. R<sub>on</sub> and R<sub>off</sub> retention failure rate is reduced by 88% and 71% respectively. R<sub>off</sub>/R<sub>on</sub> window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Fantini, L. Goux, A. Redolfi, R. Degraeve, G. Kar, Y. Chen, M. Jurczak
{"title":"Lateral and vertical scaling impact on statistical performances and reliability of 10nm TiN/Hf(Al)O/Hf/TiN RRAM devices","authors":"A. Fantini, L. Goux, A. Redolfi, R. Degraeve, G. Kar, Y. Chen, M. Jurczak","doi":"10.1109/VLSIT.2014.6894433","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894433","url":null,"abstract":"We present a systematic investigation of the impact of aggressive lateral and vertical TiN/Hf(Al)O/Hf/TiN RRAM cells stack scaling down to 10nmx10nm cell size and 5nm thickness on performance and reliability. We demonstrate that median values and 1-sigma dispersion of programming voltages, resistances and disturb are not affected by lateral and vertical scaling in agreement with QPC/hour glass conduction model. We also demonstrate that endurance robustness is instead adversely affected by both a reduction of total stack thickness and lateral cell size, the latter probably due to a reduction of the available ion supply in the oxygen exchange layer (OEL) as consequence of scaling.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125195978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ahn, Zizhen Jiang, Chi-Shuen Lee, Hong-Yu Chen, Jiale Liang, L. Liyanage, H. Wong
{"title":"A 1TnR array architecture using a one-dimensional selection device","authors":"C. Ahn, Zizhen Jiang, Chi-Shuen Lee, Hong-Yu Chen, Jiale Liang, L. Liyanage, H. Wong","doi":"10.1109/VLSIT.2014.6894404","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894404","url":null,"abstract":"Phase-change memory (PCM) cells on a single carbon nanotube field-effect transistor (CNFET) are demonstrated toward the realization of the 1TnR array architecture. The use of CNFET as one-dimensional selector, which exhibits ultra-low leakage (<; 1 pA) and large ON/OFF ratio (> 106) at high current densities, enables the cost-effective PCM cell to operate with a wide voltage margin in large 2D arrays. Uniform electrical characteristics of PCM cells over 100 cycles are obtained with the ON/OFF ratio of ~ 100 and the low SET/RESET currents of <; 1 μA.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"2 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116888406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Miyoshi, T. Ueno, K. Akiyama, Y. Hirota, T. Kaitsuka
{"title":"In-situ contact formation for ultra-low contact resistance NiGe using carrier activation enhancement (CAE) techniques for Ge CMOS","authors":"H. Miyoshi, T. Ueno, K. Akiyama, Y. Hirota, T. Kaitsuka","doi":"10.1109/VLSIT.2014.6894409","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894409","url":null,"abstract":"We first achieved ultra-low NiGe specific contact resistivities (ρ<sub>c</sub>'s) of 2.3×10<sup>-9</sup>Ωcm<sup>2</sup> and 1.9×10<sup>-8</sup>Ωcm<sup>2</sup>, which were both reduced from the best values ever reported by one order of magnitude, for Ge P- and N-MOS, respectively. The keys to the excellent performance were carrier activation enhancement (CAE) techniques using Ge pre-amorphization implant (PAI) or laser anneal (LA) followed by an in-situ contact process. Impact of ultra-low ρ<sub>c</sub>'s on saturation drive current (Id<sub>sat</sub>) was also simulated for ITRS 2015 HP nFinFET.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115611737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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