Process technology scaling in an increasingly interconnect dominated world

Abstract

The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.