K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, R. Xie, H. Shang, E. Alptekin, D. Bae, G. Bae, C. Boye, H. Cai, D. Chanemougame, R. Chao, K. Cheng, J. Cho, K. Choi, B. Hamieh, J. Hong, T. Hook, L. Jang, J. Jung, R. Jung, D. Lee, B. Lherron, R. Kambhampati, B. Kim, H. Kim, K. Kim, T. Kim, S. Ko, F. Lie, D. Liu, H. Mallela, E. Mclellan, S. Mehta, P. Montanini, M. Mottura, J. Nam, S. Nam, F. Nelson, I. Ok, C. Park, Y. Park, A. Paul, C. Prindle, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze, S. Seo, J. Shearer, R. Southwick, R. Sreenivasan, S. Stieg, J. Strane, X. Sun, M. Sung, C. Surisetty, G. Tsutsui, N. Tripathi, R. Vega, C. Waskiewicz, M. Weybright, C. Yeh, H. Bu, S. Burns, D. Canaperi, M. Celik, M. Colburn, H. Jagannathan, S. Kanakasabaphthy, W. Kleemeier, L. Liebmann, D. Mcherron, P. Oldiges, V. Paruchuri, T. Spooner, J. Stathis, R. Divakaruni, T. Gow, J. Iacoponi, J. Jenq, R. Sampson, M. Khare
{"title":"一种用于低功耗和高性能应用的10nm平台技术，其特点是在块体和SOI上具有多工作功能栅极堆栈的FINFET器件","authors":"K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, R. Xie, H. Shang, E. Alptekin, D. Bae, G. Bae, C. Boye, H. Cai, D. Chanemougame, R. Chao, K. Cheng, J. Cho, K. Choi, B. Hamieh, J. Hong, T. Hook, L. Jang, J. Jung, R. Jung, D. Lee, B. Lherron, R. Kambhampati, B. Kim, H. Kim, K. Kim, T. Kim, S. Ko, F. Lie, D. Liu, H. Mallela, E. Mclellan, S. Mehta, P. Montanini, M. Mottura, J. Nam, S. Nam, F. Nelson, I. Ok, C. Park, Y. Park, A. Paul, C. Prindle, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze, S. Seo, J. Shearer, R. Southwick, R. Sreenivasan, S. Stieg, J. Strane, X. Sun, M. Sung, C. Surisetty, G. Tsutsui, N. Tripathi, R. Vega, C. Waskiewicz, M. Weybright, C. Yeh, H. Bu, S. Burns, D. Canaperi, M. Celik, M. Colburn, H. Jagannathan, S. Kanakasabaphthy, W. Kleemeier, L. Liebmann, D. Mcherron, P. Oldiges, V. Paruchuri, T. Spooner, J. Stathis, R. Divakaruni, T. Gow, J. Iacoponi, J. Jenq, R. Sampson, M. Khare","doi":"10.1109/VLSIT.2014.6894342","DOIUrl":null,"url":null,"abstract":"A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"89","resultStr":"{\"title\":\"A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI\",\"authors\":\"K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, R. Xie, H. Shang, E. Alptekin, D. Bae, G. Bae, C. Boye, H. Cai, D. Chanemougame, R. Chao, K. Cheng, J. Cho, K. Choi, B. Hamieh, J. Hong, T. Hook, L. Jang, J. Jung, R. Jung, D. Lee, B. Lherron, R. Kambhampati, B. Kim, H. Kim, K. Kim, T. Kim, S. Ko, F. Lie, D. Liu, H. Mallela, E. Mclellan, S. Mehta, P. Montanini, M. Mottura, J. Nam, S. Nam, F. Nelson, I. Ok, C. Park, Y. Park, A. Paul, C. Prindle, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze, S. Seo, J. Shearer, R. Southwick, R. Sreenivasan, S. Stieg, J. Strane, X. Sun, M. Sung, C. Surisetty, G. Tsutsui, N. Tripathi, R. Vega, C. Waskiewicz, M. Weybright, C. Yeh, H. Bu, S. Burns, D. Canaperi, M. Celik, M. Colburn, H. Jagannathan, S. Kanakasabaphthy, W. Kleemeier, L. Liebmann, D. Mcherron, P. Oldiges, V. Paruchuri, T. Spooner, J. Stathis, R. Divakaruni, T. Gow, J. Iacoponi, J. Jenq, R. Sampson, M. Khare\",\"doi\":\"10.1109/VLSIT.2014.6894342\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. 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Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"89\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894342\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894342","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.
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