Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement

Abstract

We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO_x/WO_x bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10⁷ to 10⁹. R_on and R_off retention failure rate is reduced by 88% and 71% respectively. R_off/R_on window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.