Y. Meng, X. Xue, Y. L. Song, J. G. Yang, B. Chen, Y. Y. Lin, Q. Zou, R. Huang, J. Wu
{"title":"电阻式开关存储器快速降压集算法,编程能量低,可靠性显著提高","authors":"Y. Meng, X. Xue, Y. L. Song, J. G. Yang, B. Chen, Y. Y. Lin, Q. Zou, R. Huang, J. Wu","doi":"10.1109/VLSIT.2014.6894435","DOIUrl":null,"url":null,"abstract":"We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO<sub>x</sub>/WO<sub>x</sub> bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10<sup>7</sup> to 10<sup>9</sup>. R<sub>on</sub> and R<sub>off</sub> retention failure rate is reduced by 88% and 71% respectively. R<sub>off</sub>/R<sub>on</sub> window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement\",\"authors\":\"Y. Meng, X. Xue, Y. L. Song, J. G. Yang, B. Chen, Y. Y. Lin, Q. Zou, R. Huang, J. Wu\",\"doi\":\"10.1109/VLSIT.2014.6894435\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO<sub>x</sub>/WO<sub>x</sub> bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10<sup>7</sup> to 10<sup>9</sup>. R<sub>on</sub> and R<sub>off</sub> retention failure rate is reduced by 88% and 71% respectively. R<sub>off</sub>/R<sub>on</sub> window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894435\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement
We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 107 to 109. Ron and Roff retention failure rate is reduced by 88% and 71% respectively. Roff/Ron window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.