利用载流子活化增强(CAE)技术原位形成超低接触电阻的Ge CMOS

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI:10.1109/VLSIT.2014.6894409

H. Miyoshi, T. Ueno, K. Akiyama, Y. Hirota, T. Kaitsuka

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引用次数: 31

摘要

我们首先实现了超低的nge比接触电阻率(ρc’s) 2.3×10-9Ωcm2和1.9×10-8Ωcm2，这两个值分别比以往报道的最佳值降低了一个数量级。采用Ge预非晶化植入(PAI)或激光退火(LA)的载流子活化增强(CAE)技术，然后采用原位接触工艺，是实现优异性能的关键。并对ITRS 2015 HP nFinFET超低ρc对饱和驱动电流(Idsat)的影响进行了仿真。

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In-situ contact formation for ultra-low contact resistance NiGe using carrier activation enhancement (CAE) techniques for Ge CMOS

We first achieved ultra-low NiGe specific contact resistivities (ρ_c's) of 2.3×10^-9Ωcm² and 1.9×10^-8Ωcm², which were both reduced from the best values ever reported by one order of magnitude, for Ge P- and N-MOS, respectively. The keys to the excellent performance were carrier activation enhancement (CAE) techniques using Ge pre-amorphization implant (PAI) or laser anneal (LA) followed by an in-situ contact process. Impact of ultra-low ρ_c's on saturation drive current (Id_sat) was also simulated for ITRS 2015 HP nFinFET.

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来源期刊

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

CiteScore

3.40

自引率

0.00%

发文量