Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Hong-Yu Chen, B. Gao, Haitong Li, Rui Liu, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Zizhen Jiang, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang, Shimeng Yu, Y. Nishi, H. Wong
{"title":"Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays","authors":"Hong-Yu Chen, B. Gao, Haitong Li, Rui Liu, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Zizhen Jiang, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang, Shimeng Yu, Y. Nishi, H. Wong","doi":"10.1109/VLSIT.2014.6894434","DOIUrl":null,"url":null,"abstract":"3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13

Abstract

3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.
迈向高速、容写干扰的3D垂直RRAM阵列
由于涉及到额外的尺寸,3D RRAM阵列比2D RRAM阵列遭受更严重的可靠性问题。本文系统地评估了三维垂直RRAM阵列的单元位置依赖的写访问(选定单元)和干扰问题(未选定单元)。通过实验和模拟的结合,开发了一种方法,通过进行单设备测量来实现阵列级评估,而无需制造完整的3D阵列。基于该评价方法,在最坏情况下,双侧偏置(DSB)方案将写干扰容错性提高了1800倍,并将写延迟降低了19%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
CiteScore
3.40
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信