Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI:10.1109/VLSIT.2014.6894429

J. C. Liu, D. Yaung, J. Sze, C. Wang, Gene Hung, C. Wang, T. Hsu, R. Lin, T. Wang, W. D. Wang, H. Cheng, J. Lin, S. Tsai, S. Tsai, C. Chuang, W. Hsu, S. Y. Chen, K. C. Huang, W. H. Wu, S. Takahashi, Y. Tu, C. Tsai, R. Lee, W. P. Mo, F. J. Shiu, Y. Chao, S. Wuu

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引用次数: 16

Abstract

This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor performance can be significantly minimized. In addition, for the first time, the degradation of stacked pixel performance during the folded circuit operation under sensor array is found and improved. The final stacked sensor exhibits the comparable pixel performances to conventional BSI. Furthermore, stacked architecture provides the opportunity to enhance sensor performance by the separate process tuning for sensor wafers (without any effect on ASIC wafers), leading to a further improvement of dark performance.

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先进的1.1um像素CMOS图像传感器，3D堆叠架构

本文介绍了一种先进的1.1um像素后照CMOS图像传感器，该传感器具有3D堆叠结构。传统BSI中的载流子晶圆被ASIC晶圆取代，ASIC晶圆包含一部分外围电路，通过键合技术与传感器晶圆连接。通过适当的布局设计和工艺改进，3D连接(Through Via, TV)对传感器性能的影响可以显着降到最低。此外，首次发现并改善了传感器阵列下折叠电路工作时堆叠像素性能下降的问题。最终的堆叠传感器显示出与传统BSI相当的像素性能。此外，堆叠架构通过对传感器晶圆进行单独的工艺调整(对ASIC晶圆没有任何影响)提供了提高传感器性能的机会，从而进一步提高了暗性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

CiteScore

3.40

自引率

0.00%

发文量