H. Mertens, R. Ritzenthaler, A. Hikavyy, J. Franco, J. Lee, D. Brunco, G. Eneman, L. Witters, J. Mitard, S. Kubicek, K. Devriendt, D. Tsvetanova, A. Milenin, C. Vrancken, J. Geypen, H. Bender, G. Groeseneken, W. Vandervorst, K. Barla, N. Collaert, N. Horiguchi, A. Thean
{"title":"Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins","authors":"H. Mertens, R. Ritzenthaler, A. Hikavyy, J. Franco, J. Lee, D. Brunco, G. Eneman, L. Witters, J. Mitard, S. Kubicek, K. Devriendt, D. Tsvetanova, A. Milenin, C. Vrancken, J. Geypen, H. Bender, G. Groeseneken, W. Vandervorst, K. Barla, N. Collaert, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2014.6894360","DOIUrl":null,"url":null,"abstract":"We present a comprehensive study of Si0.55Ge0.45-cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ~2× higher hole mobility, ~2× better ION/IOFF, and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive current and hole mobility on both SiGe thickness and device width are examined in detail. This analysis shows that SiGe thickness conformality and epitaxial facet control are crucial for the optimization of SiGe-cladded FinFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
We present a comprehensive study of Si0.55Ge0.45-cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ~2× higher hole mobility, ~2× better ION/IOFF, and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive current and hole mobility on both SiGe thickness and device width are examined in detail. This analysis shows that SiGe thickness conformality and epitaxial facet control are crucial for the optimization of SiGe-cladded FinFETs.