接触和局部互连尺度对逻辑性能的影响

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI:10.1109/VLSIT.2014.6894406

S. Datta, R. Pandey, A. Agrawal, S. Gupta, R. Arghavani

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引用次数: 11

摘要

我们对金属- si和金属-绝缘体- si (MIS)触点进行了比较分析，并量化了触点/通孔电阻对逻辑性能的影响。我们的研究结果表明，与理想触点相比，硅化触点在nFinFET (ION)的ON电流中占32%的衰减。导致肖特基势垒高度降低的MIS触点在等能下提供了12%的性能增益。技术缩放到5nm将使MIS接触贡献35%的整体外部电阻，金属电阻贡献上升到20%。

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Impact of contact and local interconnect scaling on logic performance

We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.

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来源期刊

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

CiteScore

3.40

自引率

0.00%

发文量