J. Y. Wu, M. Lee, W. Khwa, H. C. Lu, H. Li, Y. Chen, M. BrightSky, T. S. Chen, T. Wang, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam
{"title":"一种采用新型后台存储方案的双密度双模相变存储器","authors":"J. Y. Wu, M. Lee, W. Khwa, H. C. Lu, H. Li, Y. Chen, M. BrightSky, T. S. Chen, T. Wang, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam","doi":"10.1109/VLSIT.2014.6894382","DOIUrl":null,"url":null,"abstract":"Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A double-density dual-mode phase change memory using a novel background storage scheme\",\"authors\":\"J. Y. Wu, M. Lee, W. Khwa, H. C. Lu, H. Li, Y. Chen, M. BrightSky, T. S. Chen, T. Wang, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam\",\"doi\":\"10.1109/VLSIT.2014.6894382\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894382\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894382","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A double-density dual-mode phase change memory using a novel background storage scheme
Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.